MRAM Sense Amplifier Offset Cancellation via Capacitor Storage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Designing a sense amplifier for magnetoresistive random access memory (MRAM) that effectively detects the small difference in resistance at a low voltage is challenging due to FET mismatch between transistors, which affects read accuracy and robustness.

Innovation Solution

A two-stage sense amplifier circuit is introduced, featuring a first stage that generates a voltage difference and a second stage with a comparator and capacitors that self-cancels FET device mismatch during a compensation phase, amplifying the difference and compensating for device mismatch using stored voltage differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a sense amplifier is designed to detect small resistance differences at low voltage in MRAM, then read accuracy is improved, but FET mismatch between transistors degrades measurement precision

Engineering Contradiction:
Improveread accuracyVSAvoidread robustness
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by performing offset cancellation before the actual read operation. During a compensation phase preceding the read, the circuit pre-charges capacitors with voltages that compensate for FET mismatch. This preliminary compensation ensures that when the actual read occurs, the mismatch errors have already been corrected, improving both read accuracy and robustness without affecting the main read operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces capacitors as intermediary elements that store compensation voltages. These capacitors act as mediators between the FET mismatch problem and the read operation solution. The capacitors hold the offset compensation voltages and apply them during the read phase, effectively decoupling the mismatch correction from the actual sensing operation and improving measurement precision

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If device mismatch compensation is implemented, then measurement precision is improved, but device complexity increases due to additional capacitors and compensation circuitry

Engineering Contradiction:
Improveread accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent achieves multi-functionality by designing the second stage circuit to perform both offset cancellation and signal amplification. The same capacitors and circuit elements used for amplifying the differential signal also store and apply the compensation voltages. This eliminates the need for separate compensation circuits, improving measurement precision without proportionally increasing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the offset compensation function with the signal amplification function in the second stage. The capacitors that would traditionally only store compensation voltages are integrated into the amplification circuitry itself. This combining of functions reduces the overall circuit complexity while maintaining improved measurement precision through mismatch compensation

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10726898B1MRAM sense amplifier with second stage offset cancellation
Publication Date: 2020.07.28 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10726898B1 patent drawing
  • US10726898B1 patent drawing
  • US10726898B1 patent drawing

AI summary

A sense amplifier circuit for sensing a data state of a data cell during a read cycle is described. The circuit includes a first stage with first circuitry to output a reference voltage and a data voltage relating to the data state of the data cell. The circuit further includes a second stage with circuitry to amplify a difference between the reference voltage and the data voltage. This circuitry includes a plurality of inverters and a plurality of capacitors. The read cycle includes a compensation phase. During the compensation phase the circuitry stores, at the capacitors, a voltage difference caused by a device mismatch of the inverters. After the compensation phase the circuitry amplifies the difference between the reference voltage and the data voltage, and compensates for the device mismatch using the stored voltage difference at the capacitors.