MRAM-SRAM nvSRAM Cell Layout for Accurate AI FMA Current Sensing
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Solution Overview
Problem
Existing MRAM-based PIM architectures for artificial intelligence computation face challenges with high latency, high power consumption, and low computational accuracy due to the inefficiency of 7T1R nvSRAM cells, particularly in determining current magnitudes accurately during AI computations.
Innovation Solution
A computation apparatus and method utilizing 8T2R and 16T4R nvSRAM cells with differential circuits and MRAM cells, where each cell includes a first and second MRAM cell connected in series with access transistors, allowing for precise control of current flow and accurate computation results through a controller that sums currents from multiple cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 7T1R nvSRAM cells are used for AI computation, then area efficiency is improved, but measurement precision of current magnitude deteriorates
Solution Approach 1:
The patent divides the single MTJ cell into two separate MTJ cells (first MTJ and second MTJ) with distinct functions: one for storing weight information and the other for generating current signals. This segmentation allows the weight storage function and current generation function to be separated, enabling accurate current measurement while maintaining area efficiency through the compact 7T1R structure.
Solution Approach 2:
The patent introduces a current mirror circuit as an intermediary mechanism between the MTJ cell and the readout circuitry. The current mirror circuit accurately copies and transfers the current signal generated by the MTJ cell to the measurement node, eliminating the need for direct high-precision current measurement and solving the measurement precision problem while maintaining area efficiency.
2Use of energy by moving object
If MRAM is used as NVM for AI operations, then power efficiency is improved by cutting off power during idle periods, but write operation latency and power consumption increase
Solution Approach 1:
The patent pre-loads weight data into the MTJ cells during idle periods when power can be supplied, so that during actual AI computation the weights are already in place and ready for use. This preliminary action eliminates the need for time-consuming write operations during computation, reducing write operation latency while maintaining power efficiency through idle period power management.
3Area of stationary object
If 7T1R nvSRAM cells are used, then area efficiency is improved, but computational accuracy deteriorates due to difficulty in determining current magnitudes
Solution Approach 1:
The patent replaces direct current magnitude measurement (which is prone to errors due to finite TMR ratios) with a voltage measurement approach. By converting the current signal to a voltage signal through a transimpedance amplifier or similar circuit, the system achieves higher computational accuracy since voltage can be measured with much higher precision than current, while maintaining the area-efficient 7T1R structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances computational accuracy and maintains high power efficiency by eliminating ambiguities in current measurements, thereby improving the accuracy of artificial intelligence computations.
Implementation Method 1
When the Tunnel MagnetoResistance (TMR) ratio is small (i.e., when the difference between IHRS and ILRS is relatively small)
Data Source
AI summary
A computation apparatus includes: a plurality of nvSRAM cells; and a controller configured generating an artificial intelligence computation result per currents flowing through the nvSRAM cells, wherein each nvSRAM cell includes a first partial cell including: a differential circuit including first and second inverters; a first access transistor having a drain connected to the first output node; a second access transistor having a drain connected to the second output node; a first MRAM cell including a first selection transistor and a first magnetic tunnel junction connected in series between a CBL node and the first output node; and a second MRAM cell including a second selection transistor and a second magnetic tunnel junction connected in series between the CBL node and the second output node.