MRAM Top Electrode Connection Using Protective Sidewall Spacers

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Solution Overview

Problem

The formation of MRAM devices is challenged by high power etch processes that can damage the tunnel barrier layer, leading to electrical shorting or poor connections, and the use of multiple masking layers increases time and costs.

Innovation Solution

A simplified method involving a protective sidewall spacer layer that etches slower than the upper ILD structure, allowing a single etch process with a single masking layer to form strong electrical connections between the top electrode and conductive wire, reducing damage to the MTJ and minimizing etch processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high power etch processes are used to form connections, then etching speed and efficiency are improved, but damage to the tunnel barrier layer occurs leading to electrical shorting or poor connections

Engineering Contradiction:

Improveetching speedVSAvoidtunnel barrier layer integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A protective sidewall spacer layer is formed on the sidewalls of the MTJ structure before the etch process to prevent damage to the tunnel barrier layer during high power etching. This preliminary protective action allows aggressive etching conditions to be used while maintaining barrier integrity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective sidewall spacer layer acts as an intermediary between the etch process and the tunnel barrier layer, absorbing the harmful effects of high power etching while allowing the etch to proceed efficiently. The spacer layer is selectively removed after serving its protective function.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If multiple masking layers are used to define openings, then precision and control of the etch process are improved, but fabrication time and costs increase

Engineering Contradiction:

Improveopening definition precisionVSAvoidfabrication time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

Multiple masking functions are merged into a single masking layer by designing the etch process to selectively remove materials based on their inherent etch rate differences. The protective sidewall spacer layer combines both protection and masking functions, eliminating the need for separate masking layers.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The protective sidewall spacer layer serves multiple functions simultaneously: it protects the tunnel barrier layer from damage, acts as a selective mask during etching, and defines the opening geometry. This multi-functionality reduces the number of process steps required.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12426274B2Method for MRAM top electrode connection

Publication Date: 2025.09.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip including a memory cell overlying a substrate and comprising a top electrode. A sidewall spacer structure is disposed along sidewalls of the memory cell. The sidewall spacer structure comprises a first spacer layer on the memory cell, a second spacer layer around the first spacer layer, and a third spacer layer around the second spacer layer. The second spacer layer comprises a lateral segment adjacent to a vertical segment. The lateral segment abuts the top electrode and has a top surface aligned with or disposed below a top surface of the top electrode. A first conductive structure overlies the memory cell and contacts the lateral segment and the top electrode.