Buried Gate MTJ Memory Device Seam Prevention
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Solution Overview
Problem
Conventional magnetic tunnel junction (MTJ) elements in semiconductor memory devices often suffer from deteriorated characteristics due to seams or irregularities in the via structure, particularly when formed on slopes or steps, which can affect their performance.
Innovation Solution
The semiconductor memory device incorporates a buried gate structure with a flat lower electrode, formed using chemical mechanical polishing (CMP) to prevent seams and irregularities, ensuring the MTJ element is formed on a planar surface, thereby improving its characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If tungsten is deposited by CVD to form a via, then the via can be formed, but seams occur in the via causing deteriorated MTJ element characteristics
Solution Approach 1:
A barrier metal layer is introduced as an intermediary between the gate electrode and the tungsten via. This barrier metal layer prevents direct contact between the gate and via materials, eliminating seam formation while maintaining electrical connectivity. The barrier layer acts as a mediating interface that resolves the contradiction between via formation ease and seam prevention.
Solution Approach 2:
The via structure is segmented into multiple layers: a lower electrode layer, a barrier metal layer, and a tungsten via layer. This segmentation allows each layer to perform its specific function independently, with the barrier metal layer specifically addressing the seam problem while the tungsten layer provides the conductive via function.
2Adaptability or versatility
If the MTJ element is formed on a slope or step in the via structure, then the via can accommodate gate steps, but the MTJ element characteristics deteriorate
Solution Approach 1:
The lower electrode layer and barrier metal layer are formed preliminarily before the tungsten via deposition. This preliminary action creates a flat, stable base structure that prevents slope and step formation during subsequent processing, ensuring the MTJ element forms on a planar surface with optimal characteristics.
Solution Approach 2:
The lower electrode layer and barrier metal layer are formed at a uniform potential level, creating an equipotential surface that eliminates slopes and steps. This equipotential structure ensures uniform MTJ element formation across the substrate, improving reliability while maintaining adaptability to gate step variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of the MTJ element by eliminating seam-related issues, leading to improved device characteristics and reduced likelihood of step formation during the manufacturing process.
Implementation Method 1
chemical mechanical polishing (CMP) to prevent seams and irregularities, ensuring the MTJ element is formed on a planar surface
Data Source
AI summary
The semiconductor memory device includes a cell transistor having a gate insulating film deposited on an inner surface of a groove formed in an upper surface of the semiconductor substrate, a gate electrode buried in the groove with the gate insulating film formed on the inner surface thereof, and a source region and a drain region formed on an upper surface of the active area of the semiconductor substrate on opposite sides of the gate electrode. The semiconductor memory device includes an MTJ element having a variable resistance that varies with a direction of magnetization that is provided on the source region and electrically connected to the source region at a first end thereof.