Magnetic Tunnel Junction Contact Plug Surface Roughness Control

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Solution Overview

Problem

Semiconductor memory devices require higher density, lower power consumption, and nonvolatile properties to meet the demands of portable computing and wireless communication devices, which existing magnetic memory technologies have not adequately addressed.

Innovation Solution

A semiconductor memory device design incorporating a selection transistor, an interlayered insulating layer, a lower contact plug, and a magnetic tunnel junction pattern with a specific metal pattern and capping metal pattern configuration to enhance electric characteristics and data storage capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a magnetic tunnel junction structure is used to achieve higher density and nonvolatile properties, then storage density and data retention are improved, but surface roughness increases which deteriorates electric characteristics

Engineering Contradiction:
Improvestorage densityVSAvoidsurface roughness
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

A capping metal pattern is introduced as an intermediary layer between the lower contact plug metal pattern and the magnetic tunnel junction bottom electrode. This capping layer serves as a mediator that provides a flat surface for the MTJ while maintaining the electrical connection through the underlying metal pattern with larger surface area

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The lower contact plug is segmented into two distinct metal patterns: a first metal pattern with larger surface area for electrical connection, and a second metal pattern with smaller surface area providing a flat capping surface. This segmentation allows each layer to optimize its function independently

Inventive Principle:
Principle #1Segmentation

2Reliability

If the metal pattern surface area is increased to improve electrical characteristics, then conductivity is improved, but the surface roughness transferred to the MTJ increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidsurface roughness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The contact plug metal is divided into two segments with different surface areas: the first metal pattern has a larger surface area optimized for electrical connection and conductivity, while the second metal pattern has a smaller surface area that provides a flat capping surface. This segmentation decouples the conflicting requirements of electrical performance and surface flatness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the contact plug structure are assigned different qualities: the lower metal pattern region is optimized for electrical conductivity with larger surface area, while the upper capping metal pattern region is optimized for providing a flat surface with smaller surface area. Each region performs its specific function with appropriate local properties

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed design improves electric characteristics and reliability of semiconductor memory devices by optimizing the structure of the magnetic tunnel junction pattern, leading to enhanced data storage and reduced surface roughness, which addresses the need for higher density and lower power consumption.

Implementation Method 1

An example data storing mechanism for a magnetic memory device is a tunnel magneto resistance (TMR) effect of a magnetic tunnel junction (MTJ)

Methodology Applied
Scientific EffectTunnel magneto resistance (TMR) effect: Magnetoresistance

Data Source

PatentUS10504960B2Semiconductor memory devices
Publication Date: 2019.12.10 SAMSUNG ELECTRONICS CO LTD
  • US10504960B2 patent drawing
  • US10504960B2 patent drawing
  • US10504960B2 patent drawing

AI summary

A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.