MTJ Device Offset Copper Pad Integration

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Solution Overview

Problem

Integrating magnetic random access memory (MRAM) and logic processes on the same wafer is challenging due to surface roughness issues and series resistance in magnetic tunnel junction (MTJ) devices, which affect the tunneling magnetoresistance and interlayer dielectric portions.

Innovation Solution

Implementing a bottom cap layer before the copper damascene process and directly contacting the bottom electrode to the copper pad, while offsetting the MTJ device from the copper pad to reduce surface roughness and avoid series resistance, and performing MRAM processes before logic processes to minimize damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bottom vias are used to connect MTJ elements to copper pads, then electrical connection is established, but series resistance increases degrading TMR

Engineering Contradiction:

ImproveTMRVSAvoidseries resistance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent removes the bottom via structure from the MTJ device architecture, directly contacting the bottom electrode to the copper pad. This extraction of the problematic intermediate via layer eliminates the additional series resistance that would otherwise degrade the TMR ratio, while maintaining electrical connectivity through direct contact.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs the copper damascene process and forms the copper pad before fabricating the MTJ device structure. By establishing the copper pad in advance and directly contacting the bottom electrode to it, the design eliminates the need for subsequent via formation that would introduce series resistance, preventing the problem before it arises.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If MRAM processes are performed earlier in the sequence, then MTJ elements can be formed, but recesses are created in ILD portions of logic areas

Engineering Contradiction:

Improveintegration of MRAM and logicVSAvoidILD recesses

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs all copper damascene processes and forms all copper pads and interconnect structures before fabricating the MTJ device stack. By completing the copper infrastructure in advance, the subsequent MRAM processes can be performed without causing recesses in the ILD, as the copper structures are already in place and protected.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent inverts the conventional process sequence by performing logic/copper processes before MRAM processes, rather than the traditional approach of forming MTJ elements first. This reversal of the process order allows copper damascene to be completed before MRAM fabrication, preventing ILD recesses while maintaining full integration capability.

Inventive Principle:

Principle #13The other way round (Inversion)

3Productivity

If logic processes are performed earlier in the sequence, then logic elements can be formed, but surface roughness increases in MRAM areas

Engineering Contradiction:

Improveintegration of MRAM and logicVSAvoidsurface roughness

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs the copper damascene process and forms smooth copper pads before fabricating the MTJ device. By establishing the copper infrastructure in advance with controlled deposition and planarization, the subsequent MRAM processes are performed on a pre-prepared surface that minimizes roughness impact on the MTJ tunnel barrier quality.

Inventive Principle:

Principle #10Preliminary action

4Device complexity

If MTJ device is placed directly over copper pad, then electrical connection is simplified, but copper surface roughness impacts MTJ performance

Engineering Contradiction:

Improveelectrical connection structureVSAvoidMTJ performance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent introduces a bottom electrode layer as an intermediary between the copper pad and the MTJ tunnel barrier. This bottom electrode serves as a mediator that decouples the MTJ structure from the copper pad surface roughness, allowing direct electrical connection while protecting the sensitive tunnel barrier from roughness-induced performance degradation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows seamless integration of MRAM and logic processes, eliminating surface roughness concerns and series resistance, thereby enhancing the performance and reliability of MTJ devices.

Implementation Method 1

A bit value stored by an MTJ element is determined by a direction of the magnetic moment of the free layer relative to a direction of a fixed magnetic moment carried by the pinned layer

Methodology Applied

Scientific EffectTunneling magnetoresistance: Magnetoresistance

Data Source

PatentUS9203013B2Magnetic tunnel junction device and fabrication

Publication Date: 2015.12.01 QUALCOMM INC

AI summary

An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.