MTJ Sidewall Volatilization for Crystallization
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Solution Overview
Problem
Magnetic tunnel junctions (MTJs) in memory devices face challenges in achieving a high magnetoresistive ratio (DRR) due to sidewall damage and crystal structure degradation during etching and encapsulation processes, especially for devices with critical dimensions below 100 nm, which affects their performance and competitiveness with other memory technologies.
Innovation Solution
A process flow that includes a high temperature anneal step and encapsulation performed sequentially in the same process chamber without breaking vacuum, allowing for crystallization of the MTJ layers and deposition of a dielectric encapsulation layer to enhance the magnetoresistive ratio while maintaining other critical device properties, using a combination of physical vapor deposition and chemical mechanical polish to form coherent lattice structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature anneal is performed to crystallize MTJ layers and improve DRR, then magnetoresistive ratio is improved, but volatile residue on sidewalls may degrade device performance
Solution Approach 1:
A volatile material layer is deposited on the sidewalls of the MTJ structure before the high temperature anneal process. This preliminary action prepares the sidewalls to withstand the subsequent high temperature treatment by providing a protective or sacrificial layer that prevents damage during crystallization, thereby enabling DRR improvement without sidewall degradation
Solution Approach 2:
The high temperature anneal process, which could potentially cause sidewall damage, is converted into a beneficial process by introducing the volatile material layer. This layer either protects the sidewalls or undergoes controlled removal to reveal improved crystal structures, transforming a potentially harmful thermal process into a beneficial crystallization treatment that enhances magnetoresistive ratio
2Reliability
If encapsulation layer is deposited to fill gaps between adjacent MTJs, then device stability is improved, but crystal structure coherence may be degraded
Solution Approach 1:
The MTJ layers are pre-crystallized through high temperature anneal before encapsulation layer deposition. This preliminary crystallization establishes coherent lattice structures in the magnetic layers, ensuring that subsequent encapsulation processing does not disrupt the crystal structure coherence while still providing the stability benefits of gap filling
Solution Approach 2:
The processing sequence is optimized by performing high temperature anneal at specific temperature ranges and durations to achieve complete crystallization before encapsulation. By controlling parameters such as anneal temperature (e.g., 400-600°C) and time, the crystal structure coherence is established and maintained, while the encapsulation layer is then deposited under conditions that preserve this coherence
3Manufacturing precision
If multiple process steps are performed between etching and encapsulation, then device properties can be optimized, but sidewall integrity is degraded
Solution Approach 1:
The volatile material deposition and high temperature anneal processes are merged into a single integrated process step. This combination allows for sidewall protection and crystal crystallization to occur simultaneously, optimizing device properties while maintaining sidewall integrity through a coordinated process rather than sequential steps that would expose sidewalls to multiple potential damage sources
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process significantly improves the magnetoresistive ratio (DRR) of MTJs without degrading other critical properties like coercivity and resistance-area product, especially for devices with dimensions below 70 nm, enhancing their performance and competitiveness with other memory technologies.
Implementation Method 1
The anneal comprises a vacuum of less than 1×10−7 Torr and a temperature between 250° C. and 350° C., and may be of sufficient duration to enable a substantial portion of the free layer, reference layer, and tunnel barrier to crystallize to a lattice matching structure
Implementation Method 2
High temperature volatilization of sidewall materials from patterned magnetic tunnel junctions
Data Source
AI summary
A process flow for forming and encapsulating magnetic tunnel junction (MTJ) nanopillars is disclosed wherein MTJ layers including a reference layer (RL), free layer (FL), and tunnel barrier layer (TB) are first patterned by reactive ion etching or ion beam etching to form MTJ sidewalls. A plurality of MTJs on a substrate is heated (annealed) at a station in a process chamber to substantially crystallize the RL, FL, and TB to a body centered cubic (bcc) structure without recrystallization from the edge of the device before an encapsulation layer is deposited thereby ensuring lattice matching between the RL and TB, and between the FL and TB. The encapsulation layer is deposited at the same station as the anneal step without breaking vacuum, and preferably using a physical vapor deposition to prevent reactive species from attacking MTJ sidewalls. Magnetoresistive ratio is improved especially for MTJs with critical dimensions below 70 nm.