MTJ Stack Redeposited Metal Removal via Dielectric Spacer
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Solution Overview
Problem
Existing methods for fabricating spin-transfer torque magneto-resistive random access memory (STT-MRAM) devices face challenges in integrating magnetic stacks into standard silicon logic and memory chips due to device degradation and short circuits caused by metal redeposition during inert ion beam etching (IBE) processing.
Innovation Solution
The method involves initial IBE processing that stops at the barrier material, followed by the formation of a dielectric spacer on the side wall of the magnetic tunnel junction (MTJ) stack, with subsequent directional etching to a bottom contact and planarization of the dielectric film, and angled-etching to trim and clean redeposited metallic materials from the barrier layer, ensuring uniform width and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If inert ion beam etching (IBE) processing is used to pattern MTJ stacks, then manufacturing precision is improved, but metal redeposition causes short circuits and device degradation
Solution Approach 1:
A dielectric spacer layer is introduced as an intermediary between the metal layers during etching. This spacer prevents direct metal-to-metal contact and serves as a barrier to metal redeposition, eliminating short circuits while preserving the precision of IBE patterning
Solution Approach 2:
The dielectric spacer is formed preliminarily before the etching process to prevent metal redeposition issues that would otherwise occur during etching. This preliminary protective action enables subsequent high-precision IBE processing without reliability penalties
2Productivity
If continuous IBE processing is used to etch through the MTJ stack, then productivity is improved, but device degradation increases due to prolonged ion exposure
Solution Approach 1:
The continuous etching process is segmented into multiple discrete steps with intermediate planarization stages. This breaks down a single long ion exposure into shorter segments, maintaining productivity while reducing cumulative device degradation through periodic process interruptions
Solution Approach 2:
The etching process employs periodic action by alternating etching steps with planarization steps. This periodic interruption allows the system to maintain high overall throughput while periodically resetting the ion exposure accumulation, thereby preserving device integrity
3Manufacturing precision
If planarization is performed before angled-etching, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The planarization step serves multiple functions: it creates a flat surface for precise angled-etching alignment, removes excess dielectric material, and prepares the surface for uniform metal deposition. This multi-functionality justifies the additional process step by delivering multiple precision benefits in one operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces device degradation and short circuits, enhancing the integration of STT-MRAM devices into wiring layers by maintaining the structural integrity of the MTJ stack and preventing conductive bridging across tunnel barriers.
Implementation Method 1
inert ion beam etching (IBE) processing
Implementation Method 2
Spin-transfer torque is an effect in which an orientation of a magnetic layer in an MTJ can be modified using a spin-polarized current
Data Source
AI summary
A spin-transfer torque magneto-resistive random access memory (STT-MRAM) device is provided. The STT-MRAM device includes a substrate, a dielectric layer and a magnetic tunnel junction (MTJ) stack. The substrate includes a conductor and a landing pad. The MTJ stack includes a reference layer element, a free layer assembly and a barrier layer element. The reference layer element is lined with redeposited metal and is disposed on the landing pad within the dielectric layer. The free layer assembly includes a free layer element, a hard mask layer element disposed on the free layer element, redeposited metal lining sidewalls of the free and hard mask layer elements and dielectric material lining the redeposited metal. The barrier layer element is interposed between and has a same width as the reference layer element and the free layer assembly.