Muller C-Element Circuit Topology for Compact Asynchronous Logic
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Solution Overview
Problem
Synchronous circuits are susceptible to side channel attacks (SCA) due to trojan circuits, and existing clockless asynchronous digital designs fail to completely remove clocks and are space inefficient.
Innovation Solution
A two-transistor level delay based circuit with nMOS and pMOS transistors configured in parallel OR configurations, coupled to active resistors, and controlled by reverse logic signals, including a semi-static cross-coupled inverter circuit, to create a Muller C-Element for asynchronous null convention logic applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous circuits are used to achieve high speed operation, then speed is improved, but susceptibility to side channel attacks increases
Solution Approach 1:
The patent replaces synchronous clocked circuits with asynchronous circuits that do not rely on global clock signals. This substitution eliminates the timing references that trojan circuits exploit for side channel attacks, while maintaining high-speed operation through event-driven handshaking protocols between circuit modules
2Object-affected harmful factors
If clockless asynchronous digital designs are used to address side channel attacks, then security is improved, but space efficiency deteriorates
Solution Approach 1:
The asynchronous circuit is divided into independent functional modules that communicate through localized handshaking signals. Each module operates autonomously without requiring global clock distribution infrastructure, reducing overall circuit area while maintaining security against side channel attacks
Solution Approach 2:
The patent employs universal asynchronous logic elements such as Muller C-elements and threshold gates that can implement multiple logic functions. These multi-functional components reduce the total number of discrete elements required, improving space efficiency while maintaining the security benefits of asynchronous operation
3Object-affected harmful factors
If traditional asynchronous circuits are used to remove clocks, then security is improved, but complete clock removal fails
Solution Approach 1:
The patent completely extracts and removes all clock signals from the digital circuit design. Asynchronous handshaking protocols replace clocked operation, eliminating the timing references that define synchronous systems. This complete removal of clocks ensures both security against side channel attacks and true asynchronous operation
Data Source
AI summary
A system comprises an nMOS active resistor, nMOS transistors, a pMOS active resistor, and pMOS transistors, wherein a subset of the nMOS transistors a subset of the pMOS transistors are coupled to each other, respectively, according to a parallel OR configuration, a source terminal of the nMOS active resistor is coupled to respective drain terminals of the nMOS transistors, and a source terminal of the pMOS active resistor is coupled to respective drain terminals of the pMOS transistors. The transistor level delay based circuit further includes a write subcircuit component includes one of the nMOS transistors coupled to at least one of the pMOS transistors, wherein the write subcircuit is controlled by reverse logic signals, and a gate component includes an additional subset of the plurality of nMOS transistors coupled to an additional subset of the pMOS transistors, the gate component corresponding to a semistatic cross coupled inverter circuit.