Multi-Address Read Operations in Low Pin Count Memory Interfaces
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Solution Overview
Problem
Serial flash memory devices face performance bottlenecks in random access due to high latency in internal sense amplifier operations, limiting their throughput in applications requiring high-speed random-access, such as execute-in-place deployments.
Innovation Solution
A memory device with a bi-directional I/O port capable of alternating between input and output modes, allowing multiple read commands and addresses to be issued before switching to output mode, optimizing throughput through protocols that manage read latency and data output phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If serial flash is used to reduce device pin count, then ease of manufacture and device simplicity are improved, but read throughput and random access performance deteriorate due to high latency in internal sense amplifier operations
Solution Approach 1:
The patent applies preliminary action by allowing the controller to issue multiple read commands and addresses before switching the I/O port to output mode. The controller receives a first address and a second address in the input mode before switching to output mode, enabling commands to be prepared and queued in advance. This overlapping of command issuance with data output reduces bus idle time and improves throughput while maintaining the low pin count architecture
Solution Approach 2:
The patent implements continuity of useful action by enabling the I/O port to operate continuously in a pipeline fashion. Multiple read operations are overlapped such that while data is being output for one address, subsequent addresses can be received and processed. The controller continuously manages the pipeline of read operations, ensuring the bus is continuously utilized without idle periods, thus maintaining high throughput despite the limited pin count
2Speed
If clock frequency is increased to improve throughput, then speed is improved, but latency from internal sense amplifier operations becomes a more significant bottleneck
Solution Approach 1:
The controller issues multiple read commands and addresses in advance before the data output phase begins. By queuing commands in the input mode before switching to output mode, the system overlaps command processing with data output, effectively hiding the sense amplifier latency. This allows the clock frequency to be increased without the latency becoming a proportionally larger bottleneck, as the pipeline continuously processes commands during the latency period
Solution Approach 2:
The patent creates continuous useful action through pipeline processing where multiple read operations are overlapped in time. The controller continuously receives addresses and manages the pipeline of read operations, ensuring that the bus is continuously utilized. This continuous operation masks the sense amplifier latency by keeping the system busy with subsequent commands during the latency period of earlier commands
3Reliability
If the I/O port switches mode after each read operation, then data output is ensured, but bus idle time increases and throughput decreases
Solution Approach 1:
The controller receives multiple addresses in advance in the input mode before switching to output mode. This preliminary action allows the system to prepare subsequent read operations while the current data is being output, eliminating the need to wait for mode switching between each operation. The bus remains continuously utilized as commands are pipelined through the system
Solution Approach 2:
The patent implements continuous useful action by overlapping multiple read operations in the pipeline. The I/O port switches mode less frequently, maintaining continuous data output and command reception without idle periods. The controller manages the pipeline to ensure smooth transitions and continuous bus utilization, eliminating the bus idle time that would result from sequential mode switching after each read operation
Data Source
AI summary
A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.