Multi-Bank Switch Scheduler for AI Interconnect Latency
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Solution Overview
Problem
Current interconnects, such as switches, in AI and HPC systems face bottlenecks due to insufficient data exchange rates, high latency, and power consumption, leading to performance limitations and increased costs from requiring multiple switches to meet communication demands.
Innovation Solution
A multi-bank memory system with a scheduler that allocates packet segments across multiple banks in ascending or descending order, allowing non-contiguous storage and efficient memory utilization, thereby reducing latency and power consumption while enhancing data exchange rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional single-bank memory is used in switches, then memory structure is simple, but data exchange rate is insufficient and latency is high
Solution Approach 1:
The memory is divided into multiple banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3) that can operate independently and in parallel. Each bank can handle packet segments simultaneously, thereby increasing the overall data exchange rate and reducing latency without requiring a completely new memory architecture.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory into multiple banks that can be accessed concurrently. This multi-bank structure adds a spatial dimension to memory operations, allowing simultaneous read/write operations across different banks, thus improving data exchange rate without proportionally increasing complexity.
2Productivity
If multiple switches are deployed to increase communication capacity, then data exchange rate is improved, but power consumption and system cost increase
Solution Approach 1:
The patent combines multiple memory banks into a single switch device, enabling parallel processing of packet segments within one switch. This consolidation achieves the communication capacity of multiple switches while avoiding the redundant power consumption and cost associated with deploying multiple separate switch units.
Solution Approach 2:
The multi-bank memory structure enables a single switch to perform multiple functions simultaneously - handling different packet segments, supporting multiple data flows, and providing redundant processing paths. This multi-functionality allows one switch to replace what would traditionally require multiple specialized switches, reducing overall power consumption.
3Productivity
If packet segments are stored contiguously in memory, then memory allocation is simple, but memory utilization is inefficient due to head-of-line blocking
Solution Approach 1:
The patent segments packets into multiple parts and stores them in different memory banks non-contiguously. For example, Packet 1's segments are stored in Bank 0 and Bank 2, while Packet 2's segments are stored in Bank 1 and Bank 3. This segmentation eliminates head-of-line blocking by allowing independent access to different packet segments across banks, significantly improving memory utilization.
Solution Approach 2:
The patent transitions from one-dimensional contiguous storage to multi-dimensional distributed storage across multiple banks. By scattering packet segments across different banks in a non-contiguous manner, the system enables parallel access patterns that improve memory utilization without requiring complex allocation algorithms.
Data Source
AI summary
Switches and methods for utilizing the switches are described. The switch has ports, a memory and a scheduler. Packets ingress and egress the switch through the ports. Each packet is divisible into packet segments. The memory includes banks. The scheduler is coupled with the ports and the memory. The scheduler is configured to allocate memory to store the packet segments in the banks such that a beginning packet segment of a packet is stored in a selected bank and each subsequent packet segment in the packet is stored in order in a next adjacent bank.