Multi-Bit Cell Read Voltage Control for State Preservation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Increasing storage density in memory systems with multi-bit cells leads to increased power consumption and data access errors due to the need for additional processing and circuits, which can alter the intermediate resistance levels during read operations.
Innovation Solution
A memory system that adjusts read voltages to simultaneously read and reprogram multi-bit cells, using an offsetting pulse to maintain the intermediate state without a separate reprogramming pulse, thereby reducing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit cells are used to increase storage density, then storage capacity is improved, but power consumption increases due to additional processing and circuits
Solution Approach 1:
The patent combines the read operation and reprogramming operation into a single integrated process. The read voltages applied to multi-bit cells simultaneously perform both data reading and state reprogramming functions, eliminating the need for separate reprogramming pulses and reducing overall power consumption.
Solution Approach 2:
The read voltage mechanism is designed to serve multiple functions: it reads the stored data from multi-bit cells and simultaneously reprograms intermediate states. This multi-functional approach reduces the number of separate operations needed, thereby lowering power consumption while maintaining high storage density.
2Quantity of substance
If multi-bit cells are used to increase storage density, then storage capacity is improved, but data access errors increase due to altered intermediate resistance levels
Solution Approach 1:
The patent applies reprogramming voltages during the read operation to proactively maintain intermediate resistance levels before they can be altered or degraded. This preliminary corrective action ensures that the multi-bit cells remain in their correct intermediate states throughout the read process, preventing data access errors.
Solution Approach 2:
The system uses feedback mechanisms to detect and correct alterations in intermediate resistance levels during read operations. By continuously monitoring and adjusting the cell states based on read results, the system maintains data integrity and reliability even when using multi-bit cells with intermediate states.
3Reliability
If separate reprogramming pulses are used to maintain intermediate states, then data accuracy is improved, but latency increases
Solution Approach 1:
The patent merges the read operation and reprogramming operation into a single simultaneous process. By applying read voltages that also serve as reprogramming voltages, the system eliminates the sequential execution of separate operations, thereby reducing access latency while maintaining data accuracy through continuous intermediate state maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces energy consumption and latency by eliminating the need for a separate reprogramming pulse, while preserving the intermediate resistance levels during read operations.
Implementation Method 1
The memory devices utilize electrical energy, along with corresponding threshold levels or processing/reading voltage levels, to store and access data
Data Source
AI summary
Methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. The apparatus may be configured to determine a polarity data associated with reading data stored at a target location. In reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.