Multi-bit Non-volatile Flip-flop Shared Shadow Latch
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Solution Overview
Problem
Conventional flip-flop circuits with non-volatile shadow latches for power gating consume significant area and energy due to the need for individual shadow components for each flip-flop, leading to an overly designed architecture in systems on chip (SoCs).
Innovation Solution
A multi-bit non-volatile shadow latch is introduced, which can be shared among two or more flip-flop circuits, utilizing a non-volatile storage circuit with two pairs of non-volatile memories to store data for multiple flip-flops, optimizing area and energy consumption by using a shared read component for sequential data retrieval and a write component for simultaneous data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual non-volatile shadow latches are used for each flip-flop to enable power gating, then data retention during power gating is achieved, but area consumption and energy consumption increase significantly
Solution Approach 1:
The patent merges multiple individual non-volatile shadow latches into a single shared non-volatile shadow latch that can store data for multiple flip-flops. The shadow latch uses two pairs of non-volatile memory cells (first pair for first flip-flop data, second pair for second flip-flop data) that are simultaneously written to during power-down and sequentially read from during power-up, eliminating the need for separate shadow latches for each flip-flop and significantly reducing area consumption.
Solution Approach 2:
The shared non-volatile shadow latch is designed to serve multiple flip-flops universally. The same shadow latch infrastructure (read component, write component, and non-volatile memory pairs) handles data retention for different flip-flops, making the system more efficient by avoiding redundant components while maintaining the ability to retain data for each individual flip-flop during power gating.
2Reliability
If individual non-volatile shadow latches are used for each flip-flop, then data retention during power gating is achieved, but energy consumption increases
Solution Approach 1:
By merging the read components and write components into shared infrastructure, the patent reduces the total energy consumption associated with data backup and restore operations. The shared shadow latch eliminates redundant read and write operations that would occur with individual shadow latches, thereby reducing overall energy consumption while maintaining data retention capability.
3Area of stationary object
If a shared non-volatile shadow latch is used for multiple flip-flops, then area consumption is reduced, but data retrieval becomes sequential rather than simultaneous
Solution Approach 1:
The patent applies preliminary action by simultaneously writing data from multiple flip-flops to the shared non-volatile shadow latch during the power-down phase, before power gating occurs. This ensures that all data is prepared and stored in advance, so that during power-up, the sequential reading process can proceed efficiently without delays caused by simultaneous write conflicts or complex coordination requirements.
Data Source
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AI summary
Summarizing the invention, a non-volatile storage circuit for storing first data from a first flip-flop circuit and second data from a second flip-flop circuit when power gating is provided. The non-volatile storage circuit comprises a read component; a write component; and a first pair of non-volatile memories and a second pair of non-volatile memories connected to the read component and to the write component; wherein: the non-volatile storage circuit is configured to be connected to the first flip-flop circuit and the second flip-flop circuit; at power-down of the first flip-flop circuit and the second flip-flop circuit, the write component is configured to simultaneously write the first data to the first pair of non-volatile memories and the second data to the second pair of non-volatile memories; and at power-up of the first flip-flop circuit and the second flip-flop circuit, the read component is configured to sequentially read the first data from the first pair of non-volatile memories and the second data from the second pair of non-volatile memories.