Multi-cell Data Processor for RF Front End Signal Processing
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Solution Overview
Problem
Current processor-based solutions for digital RF front ends in multi-standard mobile terminals face challenges in meeting silicon area and power consumption requirements while lacking flexibility and fast time-to-market, as existing ASIC-based solutions are inflexible and DSP-based solutions consume excessive resources.
Innovation Solution
A data processor architecture featuring a processor engine with multiple cells, each equipped with local instruction memory and an instruction sequencer, allowing selective connection between cells for communication, is interposed between the radio frequency and baseband sections to process data and signals, enabling flexible mapping of functions across cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated ASIC blocks are used to implement required functions, then manufacturing precision and reliability are improved, but adaptability and ease of manufacture deteriorate
Solution Approach 1:
The processor is divided into multiple identical cells, each capable of independently executing instructions and performing computational tasks. This segmentation allows the system to be configured in different ways for different applications while maintaining reliable, proven cell designs.
Solution Approach 2:
Each cell in the processor array is designed to be universal and identical, capable of performing multiple functions through configuration rather than being dedicated to a single function. This enables the same hardware to adapt to different computational requirements.
2Adaptability or versatility
If conventional DSP-based solutions are used, then adaptability is improved, but use of energy and area consumption worsen
Solution Approach 1:
Multiple identical cells are merged into a single processor array that shares common resources such as interconnect structures, control logic, and memory interfaces. This consolidation reduces overall power consumption and silicon area compared to having separate DSP units for each function.
Solution Approach 2:
Each cell is designed with optimized local resources and can be configured to perform specific computational tasks efficiently. The local quality of each cell is tailored for high-performance arithmetic operations while sharing global resources reduces overall power consumption.
3Adaptability or versatility
If conventional DSP-based solutions are used, then adaptability is improved, but area consumption worsens
Solution Approach 1:
The processor architecture merges multiple computational units into a compact array of identical cells with shared interconnect and control structures, significantly reducing the silicon area required compared to conventional DSP solutions that require separate dedicated units for each function.
Solution Approach 2:
By segmenting the processor into identical, compact cells, the design achieves high adaptability without proportionally increasing area. The segmented structure allows efficient packing and sharing of resources, reducing overall silicon footprint while maintaining flexibility.
4Adaptability or versatility
If existing processor-based solutions are used, then adaptability is improved, but productivity and power consumption worsen
Solution Approach 1:
The processor is segmented into multiple parallel cells that can simultaneously execute different computational tasks, increasing overall productivity and throughput while maintaining adaptability through configurable cell operations.
Solution Approach 2:
The processor architecture enables continuous computational action across multiple cells operating in parallel, with pipelined instruction execution and overlapping operations that maximize productivity without sacrificing adaptability.
Data Source
AI summary
The exemplary embodiments of this invention provide a data processor having a processor engine composed of a plurality of processor cells, each cell including a local instruction memory and an instruction sequencer and being configured for selective connection with at least one adjacent cell enabling communication between cells. The processor engine is configured to be interposed between a radio frequency section and a baseband section to process data output from the baseband section prior to inputting the processed data to the radio frequency section, and to process signals output from the radio frequency section prior to inputting processed data to the baseband section. A plurality of communication-related functions are mapped into a corresponding plurality of regions of cells, and local instruction memory is configured to store program instructions for implementing all or a part of the associated function. As examples, one function may be a CORDIC function and another function may be a FIR filter function.