Multi-Channel Active Pattern with Liner for Parasitic Resistance Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving short channel characteristics and high current driving capacity due to limitations in gate length reduction and parasitic series resistance.
Innovation Solution
The semiconductor devices incorporate a multi-channel active pattern with specific regions and diffusion layers, along with a liner structure, to reduce parasitic series resistance and enhance current driving capacity, while the fabrication method involves forming a dummy gate pattern, pre-liner layer, and impurity supply layer to create diffusion layers with uniform thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length is reduced to achieve short channel characteristics, then device scaling is improved, but parasitic series resistance increases
Solution Approach 1:
The active pattern is divided into multiple channels (first, second, third regions) that extend in the first direction and cross the gate pattern. This segmentation allows the current to flow through multiple parallel paths, reducing the overall parasitic series resistance while maintaining short channel characteristics through the gate-controlled second region.
Solution Approach 2:
The invention transitions from a planar channel structure to a three-dimensional multi-channel structure by extending active patterns in both the second direction (crossing the gate) and the first direction (parallel to the gate). This dimensional expansion increases the effective channel area without increasing the gate length, thereby reducing parasitic resistance while maintaining short channel effects.
2Reliability
If multi-channel active pattern is formed to reduce parasitic series resistance, then current driving capacity is improved, but device complexity increases
Solution Approach 1:
The gate pattern serves multiple functions: it controls the second region (directly overlapping the gate) to provide short channel characteristics, and simultaneously controls the first and third regions (not directly overlapping) through field effect, enabling all three channels to contribute to current driving capacity. This multi-functionality increases current capacity without proportionally increasing structural complexity.
Solution Approach 2:
The first, second, and third regions are merged into a continuous multi-channel active pattern that shares common gate control and diffusion layer structures. This merging allows the device to achieve high current capacity through combined channel contributions while avoiding the complexity of completely separate channel structures.
3Reliability
If diffusion layer is formed along outer periphery of first region, then parasitic series resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
A liner is formed on the lateral surfaces of the first region before the diffusion layer formation process. This preliminary liner structure serves as a precise template that defines the diffusion layer's position and shape, reducing the precision requirements for the subsequent diffusion process while ensuring the diffusion layer is correctly positioned along the outer periphery to minimize parasitic resistance.
Solution Approach 2:
The liner acts as an intermediary structure between the first region and the diffusion layer. It provides a well-defined interface that guides impurity diffusion along the outer periphery, making the diffusion process more controllable and less sensitive to manufacturing variations while still achieving the desired parasitic resistance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic series resistance and achieves high current driving capacity by optimizing the multi-channel active pattern and diffusion layer formation, resulting in improved short channel characteristics.
Implementation Method 1
a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration
Implementation Method 2
forming a first diffusion layer in the multi-channel active pattern not overlapping the dummy gate pattern by performing a first thermal process on the impurity supply layer at a first temperature
Data Source
AI summary
A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.