Multi-Channel Tri-Gate Architecture for GaN Power Devices
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Solution Overview
Problem
Current III-Nitride semiconductor devices face challenges in achieving reduced on-resistance, increased power density, and enhanced breakdown voltage due to insufficient gate control in multi-channel structures and degradation of 2DEG channels, which limits their performance for high-power and RF applications.
Innovation Solution
A semiconductor structure with a multi-channel tri-gate architecture that uses 3D electrodes with sidewall and planar gates to control buried channels, allowing for simultaneous gate control over multiple 2DEG channels, reducing on-resistance, and improving current handling and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple parallel conductive channels are formed within the semiconductor structure, then current density and power density are increased, but gate control over all channels becomes difficult
Solution Approach 1:
The patent transitions from planar 2D electrode contacts to three-dimensional electrodes that extend vertically through the heterostructure stack. This dimensional change enables simultaneous control of multiple parallel channels by providing top, bottom, and sidewall contact surfaces, solving the gate control difficulty while maintaining high current density through all channels.
Solution Approach 2:
The three-dimensional electrode structure nests multiple contact surfaces (top surface, bottom surface, and sidewalls) within a single vertical electrode body. This nested configuration allows the electrode to contact multiple heterostructure interfaces simultaneously, providing comprehensive gate control over stacked channels while maintaining a compact structure.
2Ease of manufacture
If 2DEG channels are positioned closer to the surface for easier access, then device fabrication is simplified, but surface traps increase causing degradation of dynamic on-resistance and reliability
Solution Approach 1:
By extending electrodes vertically into the bulk material, the patent enables access to deeply positioned 2DEG channels without requiring surface proximity. This vertical extension allows 2DEG channels to be positioned at optimal depths away from surface traps while maintaining effective electrical contact through the three-dimensional electrode structure.
Solution Approach 2:
The three-dimensional electrode acts as an intermediary that bridges the surface and deep-subsurface regions. It provides a conductive pathway that reaches down to contact buried 2DEG channels without requiring those channels to be near the surface, thus eliminating the trade-off between fabrication ease and reliability.
3Device complexity
If conventional planar electrodes are used for contact, then device structure is simpler, but control over buried channels is insufficient
Solution Approach 1:
The patent replaces planar 2D electrodes with three-dimensional electrodes that extend vertically through the heterostructure stack. This dimensional transformation provides top, bottom, and sidewall contact surfaces that simultaneously control multiple buried channels, achieving superior channel control while the vertical configuration maintains relatively simple fabrication processes.
Data Source
Figure 1a
Figure 1b
Figure 2a~2b
AI summary
The present invention relates, for example, to a semiconductor structure containing multiple parallel channels in which several parallel conductive channels are formed within the semiconductor structure. Electric contact or electrostatic control over all these channels is done by three-dimensional electrode structures. The multiple channel structure with three-dimensional electrodes can be applied to semiconductors devices such as field effect transistors, diodes, and other similar electronic or quantum-effect devices. This structure is practical for materials where multiple parallel conduction channels can be formed, such as in III-V semiconductors. Ill-Nitride semiconductors with such structures are described which can lead to increased power density, reduced on-resistance and improved device performance, in addition to reducing dynamic on-resistance, and improving the stability of their threshold voltage and reliability.