Multi-chip Detector Array for High-Resolution Imaging

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Solution Overview

Problem

The existing on-chip antenna arrays face limitations in performance due to the small size of chips operating at millimeter or terahertz frequencies, making it difficult to integrate a sufficient number of antennas for high-resolution imaging and communication systems.

Innovation Solution

A multi-chip detector apparatus is developed, where multiple single chips are arranged in inter-chip connections on a substrate, allowing for a larger antenna array by positioning additional chips alongside the first chip in rows and columns, increasing the number of antennas and pixels for improved image resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple antennas are integrated onto a single chip, then the antenna array can be implemented on-chip, but the chip size becomes excessively large

Engineering Contradiction:
Improvenumber of antennasVSAvoidchip area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The antenna array is segmented across multiple separate chips rather than integrating all antennas on a single chip. Each chip contains a subset of the total antennas, and the chips are interconnected to form a unified array, thereby distributing the spatial requirement across multiple smaller physical substrates

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from a two-dimensional integration problem on a single chip to a three-dimensional configuration involving multiple chips stacked or arranged in space. This vertical or spatial distribution allows the antenna array to achieve the required element count without proportionally increasing the area of any single chip substrate

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the chip size is increased to accommodate more antennas, then the antenna array performance improves, but the manufacturing cost and complexity increase

Engineering Contradiction:
Improveantenna array performanceVSAvoidchip integration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The antenna array system is divided into multiple independent chip modules, each containing a manageable subset of antennas. This segmentation allows for standardized manufacturing of smaller chips and simplifies the overall system integration compared to fabricating a single large-scale chip

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple identical or similar chip designs are used to create the antenna array, where each chip serves the same functional purpose. This universality enables reuse of proven designs and manufacturing processes, reducing overall system complexity and improving reliability through redundancy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10930620B2Multi-chip detector appratus
Publication Date: 2021.02.23 KOREA UNIV RES & BUSINESS FOUND
  • US10930620B2 patent drawing
  • US10930620B2 patent drawing
  • US10930620B2 patent drawing

AI summary

The present invention relates to a multi-chip detector apparatus composed of multiple single detectors. An embodiment of the invention provides a multi-chip detector apparatus having a multiple number of single chips arranged in inter-chip connection on a substrate, where the multi-chip detector apparatus includes: a first single chip that has a multiple number of single detectors formed in m rows and n columns; a second single chip that is positioned at either a left side or a right side of the first single chip and is connected row-wise with the first single chip; and a third single chip that is positioned at either an upper side or a lower side of the first single chip and is connected column-wise with the first single chip, and where the second single chip and the third single chip also have multiple numbers of single detectors formed in m rows and n columns.