Multi-chip Package Lateral Arrangement for Thinness
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Solution Overview
Problem
Multi-chip semiconductor packages face challenges in achieving lightweight, thin, and compact designs due to increased thickness and the risk of wire short-circuits and damage, particularly when incorporating controller chips and memory chips, which complicates the design and increases package size.
Innovation Solution
A novel multi-chip package design featuring a main substrate with stacked first semiconductor chips, a semiconductor package attached to the side surfaces, and a sub substrate with a mounting and connection part that extends to the main substrate, reducing wire length and using a fixing member and adhesive members to secure components, while allowing for miniaturization through a step-like chip stacking and epoxy molding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If controller chip is stacked on memory chips with long wires for electrical connection, then electrical connectivity is achieved, but package thickness increases and wire short-circuit risk increases
Solution Approach 1:
The patent transitions from a vertical stacking arrangement (controller chip on top of memory chips) to a lateral arrangement where the controller chip is positioned beside the memory chips on the same substrate plane. This dimensional change allows electrical connections to be made through short traces on the substrate rather than long wires, simultaneously reducing package thickness and preventing wire short-circuits.
2Reliability
If wires are formed long to prevent short-circuiting between controller chip and substrate wires, then wire short-circuit is prevented, but design complexity increases and package size increases
Solution Approach 1:
The patent extracts the controller chip from the vertical stacking configuration and positions it laterally beside the memory chips. This separation eliminates the need for long wires extending from the controller chip to the substrate, as connections can be made through short substrate traces, thereby simplifying the overall design and reducing package size while maintaining reliability.
3Adaptability or versatility
If multiple semiconductor chips are incorporated into one package to extend functionality, then functionality is extended, but package size and weight increase
Solution Approach 1:
The patent merges the controller chip and memory chips into a single integrated package on one substrate, with both chip types positioned laterally adjacent to each other. This unified structure extends functionality while minimizing package weight and size, as opposed to separate packages or vertical stacking that would increase overall dimensions.
Data Source
AI summary
A multi-chip package includes a main substrate; a plurality of first semiconductor chips stacked on an upper surface of the main substrate and having bonding pads which are electrically connected with the main substrate; and a semiconductor package attached to side surfaces of the stacked first semiconductor chips and electrically connected with the main substrate.