Multi-Chip Package Control Chip for Faulty Memory Selection
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Solution Overview
Problem
In multi-chip packages, if one chip fails, the sequence of external addresses becomes irregular, leading to device failure, as existing systems do not effectively select and utilize only the normally operational chips.
Innovation Solution
A multi-chip package with a control chip that includes a fuse circuit, case logic, and chip select logic to determine and select operational chips, using fuse signals and enable signals to manage chip selection and operation, ensuring normal operation even if one or more chips fail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-chip package includes multiple chips that can be selected using external addresses, then the functionality and capacity of the package is improved, but if any one chip malfunctions, the sequence of addresses becomes irregular causing failure of the package device
Solution Approach 1:
The patent applies preliminary action by pre-configuring fuse circuits in each chip that can be blown during manufacturing to mark failed chips. The control chip reads these fuse states before operation and pre-determines which chips are functional, storing this information in advance. This allows the system to bypass failed chips before address sequencing issues occur, maintaining reliable operation even when chips are defective.
Solution Approach 2:
The control chip serves as an intermediary between the external address input and the multiple memory chips. It includes an address circuit that generates enable signals, a fuse circuit that detects chip status, and a chip select logic that determines which chip to activate. This intermediary layer translates external addresses into chip-specific select signals while accounting for failed chips, preventing address sequence irregularities from causing package failure.
2Ease of operation
If external addresses are sequentially input to select chips, then the chip selection process is simplified, but the address sequence becomes irregular when a chip fails leading to device failure
Solution Approach 1:
The control chip acts as an intermediary that receives simple sequential external addresses and converts them into reliable chip selection signals. The address circuit within the control chip generates enable signals based on external addresses, while the chip select logic uses fuse circuit information to determine which chip should be activated. This intermediary processing ensures that even when chips fail, the external address input remains simple while the internal selection adapts to maintain device functionality.
Solution Approach 2:
The system changes the parameter of chip selection by transitioning from direct address-to-chip mapping to a two-stage process: first generating enable signals based on external addresses, then modifying these signals through chip select logic that considers fuse circuit states. This parameter change in the selection mechanism allows the system to maintain simple external address input while adapting internally to chip failures, preventing address sequence irregularities from causing device failure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the multi-chip package to operate normally by selectively using only the functioning chips, maintaining device functionality even when one or more chips are faulty, thereby preventing sequence irregularities and device failure.
Implementation Method 1
The first switching element reaches breaking capacity when applied with the high voltage and outputs the fuse signal as the second voltage level
Data Source
AI summary
A multi-chip package includes a plurality of memory chips and a control chip, wherein the control chip stores information about whether the memory chips are operating normally and selects chips that are operating normally according to an address signal.