Multi-Chip Semiconductor Package Layout for Pre-Verified Integration
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Solution Overview
Problem
As the degree of integration of semiconductor packages increases and their size decreases, the probability of defects in the packages also increases, making it difficult to efficiently manufacture and verify the functionality of multiple semiconductor chips without incurring significant waste due to defects.
Innovation Solution
A semiconductor package design that includes a first redistribution structure with alternately stacked layers and insulating layers, where semiconductor chips are positioned to avoid overlap, allowing for pre-verification of sub-semiconductor packages before integration, reducing the risk of defects and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the degree of integration of semiconductor packages is increased and size is decreased, then device performance and functionality are improved, but the probability of defects in the packages increases
Solution Approach 1:
The patent divides the semiconductor package into multiple independent sub-packages, each containing its own semiconductor chip and redistribution structure. This segmentation allows each sub-package to be verified independently before final assembly, reducing the overall defect probability while maintaining high integration. The package structure is split into first and second sub-packages that can be manufactured and tested separately.
Solution Approach 2:
The patent implements preliminary verification of sub-packages before final integration. Each sub-package is tested independently at an earlier stage in the manufacturing process, allowing defects to be detected and corrected before the packages are assembled together. This preliminary action reduces the risk of defects in the final integrated package.
2Adaptability or versatility
If multiple semiconductor chips are included in a semiconductor package, then device functionality and performance are improved, but the probability of defect in the package increases
Solution Approach 1:
The patent segments the multi-chip package into multiple sub-packages, each containing one or more semiconductor chips. This segmentation allows independent verification of each sub-package, so that a defect in one sub-package does not necessarily invalidate the entire package. The first and second sub-packages can be tested separately before final assembly.
Solution Approach 2:
The patent performs preliminary verification of each sub-package containing multiple semiconductor chips before final package assembly. This early testing allows defects in individual chips or their interconnections to be detected and addressed before the entire package is manufactured, reducing waste and improving yield.
3Volume of moving object
If semiconductor chips are closely integrated to decrease package size, then miniaturization is achieved, but manufacturing complexity and defect risk increase
Solution Approach 1:
The patent divides the compact multi-chip package into modular sub-packages that can be manufactured using standard processes. Each sub-package maintains a manageable complexity level while achieving overall miniaturization through vertical stacking and integrated redistribution structures. The first and second sub-packages are designed as independent modules.
4Measurement precision
If verification is performed after complete package assembly, then defect detection is possible, but manufacturing efficiency decreases due to waste from defective packages
Solution Approach 1:
The patent performs verification of sub-packages at an intermediate stage before final package assembly. This preliminary testing allows defects to be detected in individual sub-packages containing multiple chips, so that only defective sub-packages need to be discarded rather than entire packages. This significantly reduces material waste and improves manufacturing efficiency.
Solution Approach 2:
The patent enables independent verification of segmented sub-packages, allowing defect detection at the sub-package level rather than requiring complete package assembly. This segmentation facilitates earlier testing and reduces the consequences of defects, improving overall manufacturing efficiency while maintaining quality control.
Data Source
AI summary
A semiconductor package includes a first redistribution structure; a third redistribution structure electrically connected to the first redistribution structure; a first semiconductor chip disposed between the first redistribution structure and the third redistribution structure; a second semiconductor chip disposed between the first redistribution structure and the third redistribution structure; and a second redistribution structure disposed between the second semiconductor chip and the first redistribution structure, wherein the first semiconductor chip does not overlap the second redistribution structure in a direction in which the first redistribution structure and the third redistribution structure face each other.