Multi-chip Semiconductor Package with Vertical Stacking and Land Pad Array
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high input/output capability with a small footprint and flexible routing while maintaining a cost-effective manufacturing process, especially when stacking multiple chips without the need for long wirebonds or complex leadframes.
Innovation Solution
The semiconductor packages employ a reusable carrier frame and tape with a full land pad array, using routing leads to connect multiple stacked chips directly to the land pad array, and solder balls for electrical connections, allowing for flexible routing and high I/O capability without requiring a leadframe or top/bottom etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple chips are stacked with long wirebonds and complex leadframes, then electrical connections are established, but the package footprint increases and manufacturing complexity increases
Solution Approach 1:
The patent removes the traditional leadframe structure entirely, extracting only the essential function of electrical connection. Instead of using complex leadframes with multiple layers and routing, the invention uses simple land pad arrays on a substrate that directly receive solder balls from the chips, eliminating unnecessary structural complexity while maintaining electrical connectivity functionality.
Solution Approach 2:
The patent transitions from planar routing (2D) to vertical stacking (3D) by stacking multiple chips vertically and connecting them through solder balls that extend in the vertical dimension. This dimensional change allows multiple chips to be interconnected without requiring complex lateral routing paths, thereby reducing the horizontal footprint while maintaining high I/O capability.
2Ease of manufacture
If traditional leadframe and wirebond methods are used, then electrical connections are made, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent eliminates the leadframe component entirely, extracting only the essential land pad array function from the traditional leadframe structure. This simplification removes multiple manufacturing steps including leadframe formation, wire bonding, and leadframe attachment, replacing them with a simpler substrate mounting process that directly supports the chips and their solder ball connections.
Solution Approach 2:
The patent uses a simple substrate with land pad arrays that serves as a temporary or disposable mounting structure during assembly. The substrate provides the necessary electrical connection functionality without requiring the durability and complexity of traditional leadframes, allowing for simpler and more cost-effective manufacturing processes.
3Area of stationary object
If chips are connected with long wirebonds, then electrical connections are established, but the package size increases
Solution Approach 1:
The patent replaces lateral wirebond connections (horizontal dimension) with vertical solder ball connections. By stacking chips vertically and using solder balls that connect through the vertical dimension, the horizontal distance between connection points is dramatically reduced, thereby minimizing the package footprint while maintaining electrical connectivity.
Solution Approach 2:
The patent removes the wirebonding process entirely, extracting only the essential function of electrical connection. Instead of using wirebonds that extend laterally across the package, the invention uses direct solder ball connections between stacked chips, eliminating the need for long wirebonds and reducing the overall package size.
Data Source
AI summary
Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.