Multi-chip Semiconductor Package with Via Components
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Solution Overview
Problem
Current Package-on-Package (PoP) assemblies in semiconductor packaging face challenges with tight pitch stacking, large form factor, and poor warpage control, necessitating a more compact and thinner semiconductor package solution.
Innovation Solution
A multi-chip semiconductor package design featuring a lower RDL interposer with pre-fabricated via components and an upper RDL interposer that is integrally constructed on the first chip and molding compound, providing fine-pitch electrical connections and warpage reduction through the use of substrate portions and connection portions in the via components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional PoP assembly with peripheral solder balls or mold vias is used, then electrical connection between packages is achieved, but the pitch cannot be made tight and the form factor becomes large
Solution Approach 1:
The via structure is segmented into separate via components that are pre-formed and then mounted onto the substrate, rather than forming vias directly through the substrate. This segmentation allows for tighter pitch as the via components can be precisely positioned and interconnected, while reducing the overall form factor by enabling more compact routing and connection schemes.
2Reliability
If traditional PoP assembly is used, then package interconnection is achieved, but the package thickness becomes large
Solution Approach 1:
The via components are nested within the substrate structure, with the connection portions integrated into the substrate's interconnection layers. This nesting approach allows the via components to be embedded within the package thickness rather than adding to it, enabling thinner overall package design while maintaining reliable electrical interconnection between the lower and upper packages.
3Ease of manufacture
If traditional PoP assembly is used, then package structure is formed, but warpage control is poor
Solution Approach 1:
The via components have different structural characteristics in different regions: the substrate portion provides mechanical support and warpage control, while the connection portion provides electrical interconnection. This local differentiation of quality allows the package structure to be optimized for both manufacturability and warpage control, with the substrate portion acting as a stiffening element that reduces thermal and mechanical warpage.
4Manufacturing precision
If via components with substrate portion and connection portion are used, then fine pitch and reduced thickness are achieved, but device complexity increases
Solution Approach 1:
The via components serve multiple functions simultaneously: the substrate portion provides mechanical support and warpage control, while the connection portion provides electrical interconnection. This multi-functionality reduces the need for separate structural and electrical elements, thereby reducing overall device complexity despite the sophisticated via component design.
Data Source
AI summary
A multi-chip semiconductor package includes a lower RDL interposer, a first chip on the lower RDL interposer within a chip mounting area, via components mounted within a peripheral area, and a first molding compound surrounding the first chip and the via components. Each of the via components comprises a substrate portion and a connection portion coupled to the substrate portion. An upper RDL interposer is integrally constructed on the first chip, on the via components, and on the first molding compound. The upper RDL interposer is electrically connected to the connection portion of each of the via components. A second chip is mounted on the upper RDL interposer. A second molding compound surrounds the second chip.