Multi-chip Stack Shielding Layer and Conductive Bumps
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Solution Overview
Problem
The increasing complexity and miniaturization of 3D IC chip stacks lead to issues with voltage level errors, noise interference, and heat dissipation due to internal resistance and close signal line proximity, exacerbated by the integration of digital, analog, and high-frequency circuits.
Innovation Solution
A multi-chip stack structure incorporating conductive bumps and a shielding layer to conduct reference voltages and reduce electromagnetic interference, with dummy TSV structures and micro bumps used to transmit reference voltages and act as heat sinks, thereby reducing voltage errors and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chips are made thinner and stacked in more layers to achieve miniaturization, then the integration density and functionality of the IC are improved, but voltage level errors increase due to internal resistance of TSV structures
Solution Approach 1:
The power distribution network is segmented into multiple independent paths through the introduction of multiple TSV structures (first TSV, second TSV, third TSV, fourth TSV) distributed across different chips. This segmentation reduces the internal resistance of each individual path and provides multiple parallel routes for current flow, thereby reducing voltage drops and improving voltage level accuracy in the stacked chip configuration.
Solution Approach 2:
Conductive bumps are introduced as intermediary elements to establish electrical connections between the TSV structures of adjacent chips. These conductive bumps serve as mediators that transmit reference voltages and power signals through the stack, enabling the segmented TSV network to function as an integrated power distribution system across multiple chip layers.
2Area of stationary object
If signal lines of different chips are placed close together to reduce package size, then the integration density is improved, but noise interference and signal coupling between chips increase
Solution Approach 1:
Multiple TSV structures are configured to transmit reference voltages (such as power supply voltage and ground voltage) to create equipotential regions between adjacent chips. By establishing equal potential levels through the conductive bumps and TSV network, potential differences that would otherwise cause noise and signal coupling are eliminated, allowing signal lines to be placed closer together without interference.
3Adaptability or versatility
If the number of stacked layers is increased to enhance IC functionality, then the circuit integration and performance are improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat management by utilizing the vertical stacking dimension. Multiple TSV structures extend through the chip stack, providing thermal conduction paths in the vertical dimension. This allows heat generated in inner layers to be conducted outward through the TSV network to outer layers for dissipation, effectively managing heat in the third dimension and enabling higher layer counts without thermal runaway.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces voltage level errors and noise interference while enhancing heat dissipation, ensuring stable operation and reducing the operating temperature within the chip stack.
Implementation Method 1
The plurality of conductive bumps is disposed between the first chip and the second chip, and is electrically connected to the plurality of TSV structures
Implementation Method 2
The shielding layer is disposed between the first chip and the plurality of conductive bumps, and is electrically connected to the plurality of conductive bumps
Implementation Method 3
use a TSV structure to run through a silicon wafer, and use a micro bump to transmit a circuit signal to a chip of a next layer
Data Source
AI summary
A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.