Multi-chip Stacked Devices Unique ID Generation
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Solution Overview
Problem
Existing multi-chip stacked devices face challenges in communicating signals between chips with the same hardware layout, leading to reliability issues and difficulties in programming control circuits before power-up, which can prevent signal communication during the power-up sequence.
Innovation Solution
The implementation of unique identification generation connections and circuits in a multi-chip device, based on the relative position of chips in the stack, allows for targeted communication by using comparison and enable/disable logic to enable or disable recipient circuits, eliminating the need for non-volatile memory and programming mechanisms like eFuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips with the same hardware layout are stacked together, then the number of tape-outs required is reduced and development costs are lowered, but reliability issues occur and difficulties arise in programming control circuits before power-up
Solution Approach 1:
The patent applies local quality by giving each chip a unique identification code that distinguishes it from other chips with the same hardware layout. This unique ID is embedded in each chip's control circuit, allowing the base chip to selectively address and communicate with specific chips in the stack. The local differentiation through unique IDs resolves the reliability issue while maintaining the manufacturing efficiency of using identical hardware layouts across multiple chips.
Solution Approach 2:
The patent implements preliminary action by pre-programming the unique identification codes into each chip's control circuit during manufacturing, before the chips are stacked and before the device is powered up. This allows the communication channel to be properly configured and targeted from the very beginning of operation, eliminating the need for complex post-assembly programming and ensuring reliable signal communication from power-up.
2Reliability
If unique identification generation connections and circuits are implemented, then targeted communication between chips is enabled and reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a standardized unique identification generation mechanism that can be implemented in every chip with the same hardware layout. The identification generation connections and circuits use the same structural patterns and logic across all chips, allowing the system to maintain high reliability through targeted communication while avoiding the complexity of custom-designed identification systems for each chip. The universal approach reuses the same hardware resources and design patterns.
Solution Approach 2:
The patent implements self-service by enabling each chip to generate its own unique identification code using its own internal connections and circuits, rather than requiring external programming or complex centralized control. The chip's control circuit automatically generates and uses its unique ID for communication addressing, reducing the overall system complexity while maintaining reliable targeted communication.
Data Source
AI summary
Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.