Multi-Clock DAC Combining Circuit for Image Rejection
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Solution Overview
Problem
Digital-to-analog converters (DACs) generate unwanted high-frequency image signals due to discrete sampling, which can affect other circuit elements and require costly higher-order post-DAC filters or impractical increases in sampling frequency to mitigate.
Innovation Solution
A digital-to-analog conversion apparatus that combines analog outputs derived from different sampling clocks, using a combining circuit to introduce a transfer function that allows effective image rejection, enabling the use of lower-order filters like first-order low-pass filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a higher-order post-DAC filter is used to reject image signals, then image rejection performance is improved, but production cost increases
Solution Approach 1:
The patent divides the single DAC system into multiple parallel DAC channels, each operating at a lower sampling frequency. By segmenting the conversion task across multiple channels with different sampling rates (e.g., Fs and 2Fs), the image rejection burden is distributed and simplified, allowing the use of lower-order filters in each channel while achieving overall good image rejection performance.
Solution Approach 2:
The patent combines the analog outputs from multiple DAC channels operating at different sampling frequencies through a combining circuit. This merging approach allows the system to achieve effective image rejection without requiring high-order filters, as the different sampling rates naturally spread the image frequencies, enabling simpler filtering.
2Device complexity
If the sampling frequency is increased to move undesired images to higher frequencies, then the order of post-DAC filter can be reduced, but implementation becomes difficult when sampling frequency exceeds several hundred million hertz
Solution Approach 1:
Instead of using a single high-frequency DAC, the patent segments the conversion function into multiple DACs operating at different, lower sampling frequencies. This segmentation allows each DAC to operate at manageable frequencies while collectively achieving the desired spectral distribution of images, avoiding the implementation difficulties of ultra-high frequency operation.
Solution Approach 2:
The patent changes the sampling frequency parameter across multiple DAC channels, using different sampling rates (Fs, 2Fs, etc.) to distribute image frequencies in the spectrum. This parameter variation approach achieves effective image rejection without requiring any single DAC to operate at impractically high frequencies.
3Reliability
If a higher-order post-DAC filter is used, then image rejection is improved, but the complexity of the filtering system increases
Solution Approach 1:
The patent segments the filtering function by using multiple DACs with different sampling rates, which naturally distribute image frequencies across the spectrum. This segmentation allows each DAC channel to use a simple low-order filter, and the combined output achieves the image rejection that would otherwise require a complex high-order filter.
Solution Approach 2:
The patent introduces an intermediary approach by using multiple DACs operating at different sampling frequencies as mediators between the digital input and the final analog output. These intermediate DAC channels with different sampling rates naturally separate the image frequencies, allowing simple filters to effectively remove images without requiring complex high-order filtering.
Data Source
AI summary
A digital-to-analog conversion apparatus has a first digital-to-analog converter, at least one second digital-to-analog converter, and a combining circuit. The first digital-to-analog converter is arranged to receive a first sampling clock and a digital input, and convert the digital input into a first analog output according to the first sampling clock. The at least one second digital-to-analog converter is arranged to receive the digital input and at least one second sampling clock different from the first sampling clock, and convert the digital input into at least one second analog output according to the at least one second sampling clock. The combining circuit is arranged to combine the first analog output and the at least one second analog output into a combined analog output of the digital input.