Multi-Clock Reset Synchronizer for Correlated Reset De-Assertion
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Solution Overview
Problem
Current digital logic systems with multiple clock-reset pairs face inefficiencies due to uncorrelated de-assertion of resets and clocks, leading to excess leakage, routing congestion, and timing issues, particularly in synchronous and asynchronous reset synchronization circuits.
Innovation Solution
The implementation of an asynchronous multi-cycle reset synchronization circuit that correlates any number of resets and synchronous clocks for simultaneous reset de-assertion, paired with a synchronous multi-cycle reset synchronization circuit to address the limitations of single-cycle timing convergence and meta-stability uncertainties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronous reset is used to achieve precise reset timing, then reset synchronization precision is improved, but leakage power increases and routing resources are consumed
Solution Approach 1:
The reset synchronization is segmented into multiple independent asynchronous reset signals instead of using a single synchronous reset. Each asynchronous reset can be independently controlled and de-asserted, eliminating the need for continuous synchronous reset signaling that causes leakage power consumption while maintaining precise synchronization through the interlocker mechanism.
Solution Approach 2:
An interlocker mechanism is introduced as an intermediary between multiple asynchronous reset signals and the clock domain. The interlocker coordinates the de-assertion of multiple resets to ensure they all become inactive simultaneously, achieving precise reset synchronization without requiring synchronous reset circuits that consume leakage power.
2Loss of energy
If multiple asynchronous resets are used to reduce leakage power, then power consumption is reduced, but reset de-assertion becomes uncorrelated causing timing hazards
Solution Approach 1:
The interlocker mechanism implements a feedback system that monitors the state of multiple asynchronous reset signals and coordinates their de-assertion. When resets need to be de-asserted, the interlocker ensures they all transition to inactive state simultaneously, providing correlated reset de-assertion while maintaining the power benefits of asynchronous resets.
Solution Approach 2:
Multiple independent asynchronous reset signals are merged through the interlocker mechanism into a coordinated reset control system. The interlocker combines the control of multiple resets to ensure they de-assert in unison, achieving both power efficiency and reliable timing correlation.
3Speed
If single-cycle reset synchronization is used to achieve fast reset convergence, then timing speed is improved, but meta-stability uncertainty increases
Solution Approach 1:
The system dynamically adapts the reset convergence timing based on the actual state of multiple reset signals. Instead of forcing a fixed single-cycle convergence that may cause meta-stability, the interlocker mechanism allows flexible timing while ensuring all resets de-assert simultaneously, eliminating meta-stability uncertainty while maintaining fast convergence.
4Adaptability or versatility
If synchronous and asynchronous resets are used in the same circuit for flexibility, then adaptability is improved, but reset correlation becomes impossible
Solution Approach 1:
The interlocker mechanism serves as a universal interface that can handle both synchronous and asynchronous reset signals. It provides a unified method for coordinating reset de-assertion across different reset types, enabling reset correlation in circuits with mixed synchronous and asynchronous resets while maintaining the flexibility to use either reset type as needed.
Data Source
AI summary
An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.