Multi-Clock Synchronizer Circuit Without Feedback Routing
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Solution Overview
Problem
Functional errors occur in multi-clock domain systems due to unsynchronized functional signals across different clock domains, and conventional synchronizer circuits require feedback signals and additional circuitry, increasing design complexity.
Innovation Solution
A synchronizer circuit that extends and delays functional signals to synchronize them with a different clock signal without requiring feedback signals, reducing complexity by eliminating additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronizer circuits are used to synchronize functional signals across clock domains, then signal synchronization is achieved, but feedback signals and additional circuitry are required, increasing design complexity
Solution Approach 1:
The patent extracts and eliminates the feedback signal requirement from the synchronizer circuit. By using a one-way synchronization approach where the functional signal is extended and delayed without needing feedback confirmation, the circuit removes the complex feedback routing and associated circuitry that conventional synchronizers require, thereby reducing design complexity while maintaining synchronization reliability
Solution Approach 2:
The patent applies preliminary action by pre-extending the functional signal through delay elements before it reaches the second clock domain. This advance preparation of the signal timing ensures synchronization is achieved proactively without requiring feedback verification, eliminating the need for additional feedback circuitry and simplifying the overall design
2Measurement precision
If feedback signals are used in synchronizer circuits to ensure proper synchronization, then synchronization accuracy is improved, but additional circuitry and signal routing are required
Solution Approach 1:
The synchronizer circuit performs self-service by using the functional signal itself and the second clock signal to generate the synchronized output through deterministic delay and extension logic. The circuit does not require external feedback signals to verify or adjust synchronization, as the timing relationship is established through the fixed delay elements and clock domain boundaries, thereby improving synchronization accuracy without adding feedback circuitry
Data Source
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AI summary
A multi-clock domain system includes a synchronizer circuit. The synchronizer circuit includes a sequential logic circuit and a synchronizing stage. The sequential logic circuit receives a functional signal that is generated based on a first clock signal that is further associated with a first clock domain, a second clock signal that is associated with a second clock domain, and a reference signal. Based on the first and second clock signals and the reference signal, the synchronizer circuit outputs a logic signal. When the functional signal is activated, the logic signal is activated and remains activated for a predetermined time duration after the functional signal is deactivated. The synchronizing stage receives the second clock signal and further receives the logic signal from the sequential logic circuit, and outputs a synchronized functional signal.