Multi-Core Chip Test Access Using Spare Core Comparison
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Solution Overview
Problem
Comparison-based Test Access Mechanisms (TAMs) for multi-core chips with identical cores face ambiguity issues, leading to yield loss when good cores are compared with defective cores, resulting in incorrect identification and increased test time and bandwidth requirements.
Innovation Solution
A novel comparison-based TAM that reduces ambiguity by ensuring each core is compared with a sufficient number of other cores, including spare cores, using a binary model to guarantee accurate identification of defect-free cores and minimize bandwidth and test time, while incorporating diagnostic features to efficiently collect fail data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If comparison-based TAM is used to test identical cores, then test bandwidth and area costs are reduced, but yield loss occurs due to ambiguity in identifying good cores when compared with defective cores
Solution Approach 1:
The patent segments the comparison process by dividing cores into groups and performing comparisons in multiple passes. Each pass compares a subset of cores against a reference core, gradually identifying defective cores without requiring all cores to be compared simultaneously. This segmentation resolves the ambiguity by isolating defective cores step-by-step, preventing yield loss while maintaining reduced bandwidth requirements.
Solution Approach 2:
The patent applies preliminary action by selecting a reference core and comparing all other cores against it before making final yield decisions. This preliminary comparison phase identifies potentially defective cores, which are then excluded from final yield calculations. By performing this preliminary identification, the system avoids the ambiguity of comparing good cores directly with defective cores, thereby preventing yield loss while maintaining efficient bandwidth usage.
2Measurement precision
If each core is compared with every other core to eliminate ambiguity, then yield accuracy is improved, but test time increases
Solution Approach 1:
The patent segments the comprehensive comparison process into multiple passes, where each pass compares a subset of cores against a reference core. Instead of comparing all cores with all other cores simultaneously, the segmentation allows the system to identify defective cores in stages, achieving accurate identification without the full time cost of exhaustive pairwise comparisons.
Solution Approach 2:
The patent applies partial action by comparing cores against a single reference core rather than against all other cores. This partial comparison approach is sufficient to identify defective cores when combined with the multi-pass strategy, achieving the necessary measurement precision without the excessive time cost of complete pairwise comparisons.
3Reliability
If spare cores are used to mask defective cores, then yield is improved, but test complexity increases due to unorthodox test challenges
Solution Approach 1:
The patent applies self-service by using the spare cores themselves as reference cores for comparison. Instead of requiring external test equipment to manage the complexity of spare core identification, the system uses the spare cores' own responses to compare against other cores. This self-service approach simplifies the test mechanism while maintaining the yield benefits of spare core masking.
Solution Approach 2:
The patent applies universality by using the same comparison mechanism for both testing and yield evaluation. The test mechanism universally compares core responses against a reference, whether the reference is a known good core or a spare core. This multi-functional approach handles the unorthodox test challenges of spare cores without requiring separate complex test paths, thereby improving yield while controlling test mechanism complexity.
Data Source
AI summary
Exemplary system, method and computer-accessible medium for testing a multi-core chip can be provided which can have and/or utilize a plurality of identical cores. This can be performed by comparing each core with as many as at least the number of spare cores plus 1 using a comparator; the number of comparators can equal the total number of cores multiplied by one-half the number of spare cores plus 1. A mismatch between two cores can identify at least one of the two cores as defective and a perfect match between two cores can identify both cores as not defective. The multi-core chip can fail the test if the number of defective cores can be greater than the number of spare cores.