Multi-Core Processor Pipeline Configuration for Data Processing

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Solution Overview

Problem

In pipeline processing architectures, achieving optimal processing speed for diverse data units is hindered by the need for dedicated processing cores for each data type, leading to inefficiencies due to the expense of designating cores for each operation and potential overlap in operations across data types.

Innovation Solution

A multi-core processor with a classifier and distributor system that configures processing cores into selective pipelines based on data unit types and required operations, allowing cores to operate on multiple data types and dynamically assign operations to minimize processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated processing cores are designated for each data type in pipeline architecture, then processing reliability for specific data types is improved, but device complexity and resource utilization efficiency deteriorate

Engineering Contradiction:
Improveprocessing reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Processing cores are designed to be reconfigurable and can dynamically adapt to handle different data types and operations. The system uses a classification mechanism to route data units to appropriate processing pipelines, and processing cores can be dynamically assigned to different functions based on current processing needs, allowing one core to serve multiple purposes across different time periods.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The pipeline architecture implements dynamic configuration where processing cores can be selectively programmed and assigned to different processing operations based on the type of data unit being processed. This dynamic assignment allows the system to optimize processing paths for different data types without requiring permanent dedicated hardware for each data type.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If dedicated processing cores are designated for each operation, then processing precision for specific operations is improved, but loss of time due to core idle periods worsens

Engineering Contradiction:
Improveprocessing precisionVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The system maintains continuous processing by dynamically assigning processing cores to different data types and operations based on current workload requirements. When a processing core completes one type of operation, it can immediately be reassigned to handle a different operation type, eliminating idle time and ensuring continuous useful action across all processing resources.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

Processing cores are dynamically reprogrammed and reassigned based on the classification of incoming data units. This dynamic adaptation allows the system to maintain high processing precision for each operation type while minimizing idle time by quickly transitioning cores between different operational states.

Inventive Principle:
Principle #15Dynamics

3Productivity

If more processing cores are allocated to handle diverse data types, then productivity is improved, but device complexity and cost worsen

Engineering Contradiction:
Improveprocessing speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Instead of allocating separate dedicated cores for each data type, the system uses a smaller number of universal processing cores that can be dynamically configured to handle different data types. This multi-functional approach maintains high processing throughput while reducing the total number of cores required, thereby lowering device complexity and cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system segments the processing function into classification and execution phases. The classification stage identifies data unit types and required operations, then segments the execution workload by assigning specific processing tasks to appropriate processing cores. This segmentation allows efficient utilization of a smaller core set rather than requiring dedicated cores for every possible data type.

Inventive Principle:
Principle #1Segmentation

4Device complexity

If processing cores are shared across multiple data types, then device complexity is reduced, but processing time for individual data units increases

Engineering Contradiction:
Improvedevice complexityVSAvoidprocessing time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The system implements dynamic pipeline configuration where processing cores are selectively assigned to different data types based on current processing requirements. This dynamic assignment optimizes the balance between sharing resources and maintaining fast processing by creating specialized processing paths on-demand rather than using fixed static assignments.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The classification mechanism performs preliminary identification of data unit types and required operations before routing to processing cores. This preliminary action allows the system to pre-configure optimal processing paths and minimize processing time by avoiding unnecessary routing delays and core reconfiguration overhead during actual processing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9465619B1Systems and methods for shared pipeline architectures having minimalized delay
Publication Date: 2016.10.11 MARVELL ISRAEL (M L S L) LTD
  • US9465619B1 patent drawing
  • US9465619B1 patent drawing
  • US9465619B1 patent drawing

AI summary

Systems and methods are provided for a multi-core processor for processing different types of data units. A system includes a classifier configured to classify incoming data units into different type data units. A plurality of processing cores are selectably configurable into plural processing pipelines, respective processing pipelines including connected processing cores, ones of the processing cores being selectably programmed to execute a respective processing operation on a received incoming data unit, different ones of the processing pipelines defined by a selectable number of processing cores. A distributor is configured to distribute the different types of data units to one of the pipelines among the plural pipelines at least as a function of the classified type of the data units and the programmed processing operations of processing cores in the pipelines.