Multi-CTE Package Substrate Stack for Warpage Reduction
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Solution Overview
Problem
Thermal stresses induced by mismatched coefficients of thermal expansion (CTE) among materials in semiconductor packages cause warpage, affecting reliability.
Innovation Solution
The method involves laterally assembling substrates with varying CTEs and stacking them vertically to reduce CTE mismatch, using substrates with specific CTE ranges and arranging chips and sub-substrates based on their CTEs to minimize warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If various materials are applied in a semiconductor package, then the functionality and performance of the package are improved, but the mismatch of coefficient of thermal expansion (CTE) among materials causes thermal stresses and warpage during thermal processes
Solution Approach 1:
The package structure is divided into multiple substrate layers (first substrate, second substrate, third substrate) with progressively decreasing CTE values. This segmentation allows each layer to be optimized for its specific CTE range, enabling the use of diverse materials while maintaining overall structural stability and reducing warpage during thermal processes
Solution Approach 2:
Different substrate layers are assigned different CTE characteristics tailored to their specific positions and functions within the package. The first substrate has higher CTE suitable for supporting large chips, while the second and third substrates have lower CTE values for dimensional stability, allowing each region to have optimized material properties for its local requirements
2Reliability
If substrates with different CTEs are stacked vertically, then the CTE mismatch is reduced and warpage is minimized, but the manufacturing process complexity increases
Solution Approach 1:
Conductive vias are formed in the second substrate before the third substrate is assembled onto it. This preliminary action ensures proper alignment and electrical connectivity are established in advance, simplifying the subsequent assembly process and reducing manufacturing complexity despite the multi-layer structure
Solution Approach 2:
The package structure employs a nested arrangement where the third substrate with lower CTE is placed on top of the second substrate, which itself is on the first substrate. This nested configuration of progressively lower CTE layers creates a stable gradient structure that minimizes warpage while following a systematic assembly sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warpage and enhances package density by aligning CTE distributions, improving structural reliability and efficiency.
Implementation Method 1
Due to a mismatch of coefficient of thermal expansion (CTE) among the various materials, a thermal stresses induced by a later thermal process such as reflow process causes warpage
Data Source
AI summary
A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.