Multi-Cycle Path Circuit Verification for Signal Stability
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Solution Overview
Problem
There is a lack of formal verification methods for electronic circuits with multi-cycle path (MCP) designs, which require delays greater than one clock cycle, leading to potential metastability issues and undefined circuit functionality.
Innovation Solution
A method and system for formal verification of MCP circuits involving backward and forward traversal analyses to construct counter and combinational logic circuits, ensuring signal stability through a monitor circuit that checks assertions on sequential element inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the delay of the critical path is configured to be greater than the clock cycle period in an MCP circuit, then the circuit can handle complex computations requiring multiple clock cycles, but metastability may occur and circuit functionality becomes undefined
Solution Approach 1:
The patent applies preliminary action by constructing a monitor circuit before the formal verification process to proactively detect potential metastability issues. The monitor circuit is built during the verification setup phase, performing backward and forward traversal analyses to identify all signal paths that could potentially cause metastability, so that these issues can be detected and addressed before the circuit is manufactured or deployed.
Solution Approach 2:
The patent implements feedback by using the monitor circuit to continuously observe and provide information about the stability of signal paths in the MCP circuit. The formal verification process uses this feedback to determine whether the circuit design complies with stability requirements, allowing designers to iteratively refine the circuit configuration to eliminate metastability risks while maintaining multi-cycle operation.
2Measurement precision
If formal verification is performed on MCP circuits using traditional methods, then verification can be conducted, but it cannot properly verify circuits with delays greater than one clock cycle
Solution Approach 1:
The patent applies dynamics by transforming the static verification approach into a dynamic one that can adapt to multi-cycle paths. The method dynamically constructs monitor circuits based on the specific characteristics of the MCP circuit being verified, using backward traversal from sequential elements and forward traversal through combinational logic to adaptively identify and verify all relevant signal paths, regardless of their delay characteristics.
Solution Approach 2:
The patent implements parameter changes by modifying the verification parameters to account for multi-cycle operation. Instead of using fixed single-cycle verification parameters, the method adjusts the analysis to consider variable delay parameters across multiple clock cycles, allowing the verification process to properly evaluate circuits with critical path delays greater than one clock cycle period.
3Reliability
If backward and forward traversal analyses are performed to construct monitor circuits, then signal stability can be verified, but the verification process becomes complex
Solution Approach 1:
The patent applies segmentation by dividing the complex verification process into distinct phases: backward traversal analysis to identify upstream sequential elements, forward traversal analysis to identify downstream combinational logic, and monitor circuit construction. This segmentation breaks down the complex task of verifying multi-cycle path stability into manageable, systematic steps that can be automatically executed by verification tools.
Data Source
AI summary
Method includes, for a point in MCP circuit, performing backward traversal of the circuit along the COI of that point, to sequential elements directly driving that point; constructing a counter circuit for all sequential elements driving that point, and combining the constructed counter circuits to a combined logical circuit of all of the counters in the COI, to determine whether signals in the COI are stable; performing a fan out traversal of the MCP circuit from the selected point and up to next immediate sequential elements downstream in the fan out; constructing a combinational logic circuit for the combinational elements in the fan out to determine whether that combinational element blocks a signal of the signal paths when that signal is unstable, and combining the combinational logic circuits to a combined combinational logic circuit; and checking an assertion that inputs of the next immediate sequential elements are stable.