Multi-Die 3DIC Static Timing with Slack Pessimism Reduction
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Solution Overview
Problem
The increased complexity of static timing analysis in three-dimensional integrated circuits (3DICs) due to the stacking of dies results in significant processing time and resource consumption, particularly when analyzing various parameter variations.
Innovation Solution
A method for static timing analysis that selects portions of a circuit design targeted for different dies, determines timing values for each combination of corners, adjusts worst-case slack values by reducing pessimism through timing adjustment, and optimizes the analysis process to reduce computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If static timing analysis is performed on all parameter combinations for multi-die 3DICs, then timing accuracy is improved, but processing time and computational resources increase significantly
Solution Approach 1:
The patent segments the multi-die 3DIC timing analysis into two distinct phases: (1) individual die timing analysis where each die is analyzed separately for its own timing paths, and (2) cross-die timing analysis where only the inter-die timing paths are analyzed. This segmentation avoids the combinatorial explosion of analyzing all possible parameter combinations across all dies simultaneously, thereby reducing processing time while maintaining timing accuracy for both intra-die and inter-die paths.
Solution Approach 2:
The patent performs preliminary timing analysis on each individual die before performing the cross-die timing analysis. By pre-computing the timing characteristics of each die separately and caching these results, the system avoids redundant calculations when analyzing cross-die paths. This preliminary action significantly reduces the computational complexity of the subsequent cross-die analysis while preserving timing accuracy.
2Reliability
If comprehensive corner analysis is performed for each die in the stack, then timing reliability is improved, but device complexity and analysis overhead increase
Solution Approach 1:
The patent divides the timing analysis into separate segments for each die and for cross-die paths. Each die undergoes comprehensive corner analysis independently to ensure timing reliability, while the cross-die analysis leverages these individual results. This segmented approach maintains thorough reliability checking without requiring the system to manage the full complexity of all possible corner combinations across the entire 3DIC stack simultaneously.
Solution Approach 2:
The patent introduces intermediate timing results from individual die analyses as mediators for the cross-die timing analysis. Instead of directly analyzing all corner combinations across multiple dies, the system uses the pre-computed timing characteristics of each die as intermediate inputs. This intermediary step simplifies the overall analysis complexity while preserving timing reliability by ensuring that each die's comprehensive corner analysis is performed.
3Reliability
If full static timing analysis is performed on multi-die 3DICs, then timing verification completeness is improved, but memory requirements and computational power increase
Solution Approach 1:
The patent segments the timing verification into separate analyses for individual dies and for cross-die paths. This segmentation allows the system to verify timing completeness for each segment independently using manageable computational resources, rather than requiring all resources to simultaneously handle the entire multi-die system. The segmented approach ensures verification completeness while reducing peak memory and computational power requirements.
Solution Approach 2:
The patent performs preliminary timing analysis on each die separately before conducting cross-die timing verification. By pre-computing and storing the timing characteristics of individual dies, the system reduces the computational workload of the subsequent cross-die analysis. This preliminary action ensures that timing verification remains complete while significantly reducing the memory and computational power required during any single analysis phase.
Data Source
AI summary
A system performs timing analysis of three-dimensional integrated circuits (3DICs). The circuit design is targeted for implementation on a stacked die that has a plurality of dies. The circuit design includes portions of the circuit design, each portion of the targeted for a different die. The system selects a net that crosses die boundaries and determines a plurality of sets of timing values of the net. The system determines a worst case slack value for the net based on the sets of timing values. The system determines a timing adjustment value for the net based on aggregate timing values determined from the sets of timing values. The system adjusts the worst case slack value for a net based on the timing adjustment value for each load pin of the net. The adjustment of the worst case slack reduces pessimism of the worst case slack value.