Multi-Die Package Structure With Stacked Top Dies and Wire Bonding
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Solution Overview
Problem
Semiconductor electronic devices face challenges in scaling down while maintaining electrical characteristics, quality, cost, and yield, as single chips struggle to meet multifunctional and high-volume data processing needs, necessitating improved integration levels.
Innovation Solution
A package structure comprising a molded structure with multiple electronic devices, including a first and second top die, encapsulated by an encapsulant, and electrically connected through bonding pads, allowing for different functional components to be integrated efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated to meet multifunctional needs, then functionality and data processing capability are improved, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor system into multiple discrete chips (first semiconductor chip, second semiconductor chip, third semiconductor chip) that can be independently manufactured and then integrated through wire bonding. Each chip performs specific functions (logic, memory, I/O), allowing complex multifunctional capabilities to be achieved through modular assembly rather than a single complex chip, thereby managing device complexity while enhancing adaptability.
Solution Approach 2:
The patent creates a universal package structure that can accommodate different types and numbers of semiconductor chips (logic chips, memory chips, I/O chips) with different pin configurations. The wire bonding technology provides a universal interconnection method that works across various chip types, enabling the same package structure to serve multiple functions and different application requirements.
2Area of moving object
If semiconductor device dimensions are reduced for scaling, then integration density is improved, but electrical characteristics and manufacturing quality deteriorate
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing multiple semiconductor chips vertically one on top of another within a single package. This vertical arrangement allows high integration density to be achieved by utilizing the third dimension (height) rather than further reducing chip area, thereby maintaining better electrical characteristics and manufacturing precision on each individual chip while achieving high overall system density.
3Adaptability or versatility
If more electronic devices are integrated in the molded structure, then functionality is improved, but alignment precision between bonding pads becomes more difficult to maintain
Solution Approach 1:
The patent introduces wire bonding as an intermediary connection method between the bonding pads of different semiconductor chips. Instead of requiring direct mechanical or electrical contact between precisely aligned pads, the wire bonding process uses flexible metal wires that can be routed and bonded to pads with greater tolerance for misalignment. This intermediary approach enables functional integration of multiple electronic devices while relaxing the stringent alignment precision requirements.
Data Source
AI summary
A package structure, an assembly structure and a manufacturing method are provided. The package structure includes a molded structure, a first top die and a second top die. The molded structure includes a first electronic device, a second electronic device and an encapsulant encapsulating the first electronic device and the second electronic device. The first top die is electrically connected to the first electronic device and the second electronic device. The second top die is electrically connected to the second electronic device.