Multi-Die Power Semiconductor Device on Lead Frame
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Solution Overview
Problem
Conventional DC-DC converters with high-side and low-side MOSFETs on separate die paddles face challenges in heat dissipation and cost due to large die paddle areas, and the height of bonding wires must be carefully controlled to avoid contact with the low-side MOSFET, leading to poor thermal performance.
Innovation Solution
The design incorporates a lead frame unit with a die paddle and pins, where the control die is flipped and attached on carrier pins, and metal clips are used to connect the MOSFETs, allowing for improved heat dissipation by exposing the bottom surfaces of the die paddle and pins from the plastic package body, and optimizing the layout to reduce the length of bonding wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate die paddles are used for high-side MOSFET and low-side MOSFET, then electrical connection is achieved, but heat dissipation performance deteriorates and device area increases
Solution Approach 1:
The patent merges the high-side MOSFET and low-side MOSFET onto a single die paddle, allowing both power devices to share the same thermal path to the heat sink. This consolidation improves heat dissipation efficiency while reducing the overall device area compared to separate die paddle configurations.
Solution Approach 2:
The patent utilizes the vertical dimension by exposing the bottom surface of the die paddle to serve as a heat dissipation terminal. This allows heat to be conducted directly from the MOSFETs through the die paddle to the external heat sink, creating an efficient three-dimensional thermal management solution.
2Reliability
If bonding wire height is increased to connect high-side MOSFET and control device, then electrical connection is achieved, but risk of contact with low-side MOSFET increases
Solution Approach 1:
The patent introduces a metal clip as an intermediary component to establish electrical connection between the high-side MOSFET and the control device. This metal clip routing provides physical isolation and precise control over the connection path, eliminating the risk of bonding wire contact with the low-side MOSFET while maintaining reliable electrical connectivity.
3Reliability
If large die paddle area is used, then electrical connection and heat dissipation are achieved, but cost increases and device size increases
Solution Approach 1:
The patent combines both power MOSFETs on a single die paddle with optimized layout, reducing the total die paddle area required compared to separate die paddle configurations. This consolidation maintains all necessary electrical connections while minimizing the stationary object area, thereby reducing cost and device size.
Solution Approach 2:
The patent exposes only the bottom surface of the die paddle that is required for heat dissipation, rather than exposing the entire die paddle structure. This localized approach optimizes heat dissipation functionality while minimizing the overall device footprint and material usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances heat dissipation and reduces costs by minimizing the size of the device while ensuring reliable electrical connections, thereby improving the thermal performance and efficiency of the power control device.
Implementation Method 1
metal clips are used to connect the MOSFETs
Implementation Method 2
improved heat dissipation by exposing the bottom surfaces of the die paddle and pins
Implementation Method 3
exposing the bottom surfaces of the die paddle and pins from the plastic package body, thereby improving the thermal performance
Data Source
AI summary
A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.


