Multi-Die Voltage Regulation with Localized DVFS Control

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Solution Overview

Problem

Current SOC devices face challenges in efficiently managing multiple IP blocks with unique power supply requirements, leading to complex power delivery designs and inefficiencies due to significant IR drops and increased current demands during active modes.

Innovation Solution

A semiconductor device package that integrates a passive device with a power consuming device, utilizing an array of passive elements and terminals to create distinct, localized voltage regulators, allowing for fine-grained power optimization and reduced system power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple IP blocks with unique power supply requirements are integrated into SOC devices, then functionality and power optimization are improved, but device complexity and power delivery design complexity increase

Engineering Contradiction:
Improvepower supply requirementsVSAvoidpower delivery design
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The power delivery network is segmented into multiple independent voltage regulators, each serving specific IP blocks with unique power requirements. This segmentation allows each regulator to be optimized for its specific load characteristics while maintaining overall system flexibility and reducing design complexity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If higher supply voltages are provided to analog functions, then analog performance is improved, but power consumption of the overall device increases

Engineering Contradiction:
Improveanalog performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Different voltage levels are provided locally to different functional blocks based on their specific requirements. Analog functions receive higher voltages for optimal performance, while digital blocks operate at lower voltages for power efficiency. This local quality differentiation resolves the contradiction between analog performance and overall power consumption.

Inventive Principle:
Principle #3Local quality

3Reliability

If supply voltage is raised to compensate for IR drops at the last power consuming structure, then performance of distant structures is improved, but the voltage exceeds the compliance voltage tolerance of the first power consuming structure

Engineering Contradiction:
Improveperformance of last power consuming structureVSAvoidcompliance voltage tolerance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The power delivery network is divided into multiple regulated domains, each maintaining appropriate voltage levels for its specific load. This segmentation prevents excessive voltage at any single point, eliminating IR drop issues without violating compliance voltage tolerances of any power consuming structure.

Inventive Principle:
Principle #1Segmentation

4Device complexity

If a simple LDO linear regulator is used off the higher supply voltage, then implementation complexity is reduced, but power efficiency deteriorates due to significant current draw

Engineering Contradiction:
Improveregulator implementationVSAvoidpower efficiency
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

Switching regulators are employed instead of simple LDOs, fundamentally changing the operating parameters from linear voltage dropping to efficient switching conversion. This parameter change enables high power efficiency while maintaining acceptable implementation complexity through integrated switching regulator designs.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250149489A1Multi-Die Fine Grain Integrated Voltage Regulation
Publication Date: 2025.05.08 APPLE INC
  • US20250149489A1 patent drawing
  • US20250149489A1 patent drawing
  • US20250149489A1 patent drawing

AI summary

A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.