Integrated Circuit Timing Signaling for Multi-Drop Bus Arbitration Delays
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Solution Overview
Problem
The integration of multiple communication systems and subsystems in electronic devices using shared multi-drop buses leads to arbitration-related timing delays and conflicts, affecting data transmission efficiency.
Innovation Solution
Integrated circuits include information on time delays in outbound data packets and utilize a synchronization generator circuit to generate timing signals, accounting for unsuccessful arbitration attempts, allowing devices to adjust operations based on expected periodic events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple SOCs and subsystems share a multi-drop bus, then device functionality and integration are improved, but arbitration timing delays increase
Solution Approach 1:
The patent applies preliminary action by having the transmitting SOC calculate and include the arbitration delay time in advance within the data packet before transmission. The delay time is determined based on the arbitration outcome and is embedded in the packet header, allowing the receiving SOC to pre-adjust its timing expectations without waiting for additional synchronization signals.
Solution Approach 2:
The patent implements feedback by having the transmitting SOC provide delay time information back to the receiving SOC through the data packet. This feedback mechanism allows the receiving SOC to compensate for the arbitration delay by adjusting its internal timing, effectively closing the timing synchronization loop.
2Reliability
If arbitration is performed to coordinate data transmission, then data transmission correctness is improved, but transmission speed decreases
Solution Approach 1:
The arbitration delay time is fed back to the receiving SOC through the data packet, allowing it to adjust its timing expectations. This feedback mechanism maintains transmission correctness by ensuring both SOCs are synchronized despite arbitration delays, while minimizing the impact on transmission speed.
Solution Approach 2:
The patent changes the timing parameter by adjusting the receiving SOC's expected arrival time based on the included delay information. By modifying the timing parameter dynamically according to the actual arbitration outcome, the system maintains reliability without permanently reducing transmission speed.
3Measurement precision
If time delay information is included in data packets, then synchronization accuracy is improved, but packet size increases
Solution Approach 1:
The delay time is represented as a parameter within the existing packet structure, likely in the header or as a small field that can be efficiently encoded. By changing how timing information is represented and integrated into the packet format, the system achieves accurate synchronization with minimal impact on packet size.
Data Source
AI summary
Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.