Multi-drop Clock Synchronization in Multi-node Systems
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Solution Overview
Problem
Multi nodal computer systems without a clock chip per node face challenges in synchronously starting and stopping all chips, as existing methods require a central clock chip to coordinate these actions effectively.
Innovation Solution
A method where one chip is designated as a master chip, connected to slave chips via multi-drop nets and a reference clock, allowing it to send commands for synchronous start and stop operations, with each chip having internal offset counters to adjust for latency differences, and using the same multi-drop connection for both clock start and stop requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a central clock chip is used to coordinate synchronous start and stop operations, then synchronous operation of all chips is achieved, but device complexity and wiring needs increase
Solution Approach 1:
The patent removes the central clock chip from the system architecture. Instead of having a dedicated clock chip per node, the clock functionality is extracted and distributed to individual chips, with one chip per node acting as a master chip that generates and distributes clock signals to slave chips through multi-drop nets.
Solution Approach 2:
The system is segmented into master chips and slave chips, where each node has one master chip that independently manages clock distribution to its associated slave chips. This segmentation eliminates the need for a centralized clock chip while maintaining synchronous operation within each node.
2Reliability
If a central clock chip is used to coordinate synchronous start and stop operations, then synchronous operation of all chips is achieved, but device complexity increases
Solution Approach 1:
The master chip performs multiple functions: it generates clock signals, distributes them to slave chips, and coordinates synchronous start and stop operations. This multi-functionality eliminates the need for separate dedicated clock chips, reducing overall system complexity while maintaining synchronous operation.
Solution Approach 2:
Each master chip independently manages its own node's clock distribution without requiring external coordination from a central clock chip. The master chip autonomously generates and distributes clock signals to its slave chips, making the system more modular and less complex.
3Measurement precision
If separate control lines are used for clock start and stop requests, then control precision is improved, but wiring needs and device complexity increase
Solution Approach 1:
The patent combines the clock start and stop control functions into a single control line. The same multi-drop net that distributes clock signals is also used to transmit control requests, eliminating the need for separate control lines while maintaining precise control through protocol-based command differentiation.
Solution Approach 2:
The control line serves multiple functions: it transmits both clock start and stop requests, and also carries data between master and slave chips. This multi-functional use of the control line reduces wiring complexity while maintaining control precision through protocol-based signal differentiation.
Data Source
AI summary
A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.