Multi-FPGA Timing Analysis via Graph Segmentation
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Solution Overview
Problem
Current methods are unable to perform a complete timing analysis of multi-FPGA boards due to the high computational power and memory requirements, limiting the determination of the maximum permissible clock frequency for the entire system.
Innovation Solution
An automated method is implemented to analyze the timing of an integrated circuit on an electronic board with interconnected FPGA chips by setting up a graph representing inter-chip and intra-chip portions, determining travel times, and adjusting for delays introduced by logic cells and physical tracks, including the use of serializers and deserializers to correct synchronization violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complete timing analysis model of the entire multi-FPGA board is created, then timing analysis precision is improved, but computational power and memory requirements become excessively high
Solution Approach 1:
The patent divides the multi-FPGA board into individual FPGA components and analyzes timing for each FPGA separately using graph representations. Instead of creating one massive model of the entire board, the system segments the analysis into manageable per-FPGA portions, determining travel times for intra-FPGA and inter-FPGA paths independently and then combining results to achieve complete board timing analysis with reduced computational burden
2Measurement precision
If a complete timing analysis model of the entire multi-FPGA board is created, then timing analysis precision is improved, but memory capacity requirements become excessively high
Solution Approach 1:
The patent segments the timing analysis into individual FPGA components, creating separate graph representations for each FPGA rather than one comprehensive board-level model. This segmentation reduces memory requirements by analyzing smaller, manageable portions independently and combining results, while still achieving complete board timing coverage
3Device complexity
If only intra-FPGA timing analysis is performed, then computational complexity is reduced, but synchronization path analysis across the entire board is incomplete
Solution Approach 1:
The patent introduces an intermediary approach by representing inter-FPGA connections as graph links with associated travel times. This allows the system to extend intra-FPGA timing analysis to board-level analysis by treating inter-FPGA paths as additional graph edges, enabling complete synchronization path analysis across chip boundaries while maintaining the computational efficiency of graph-based methods
Solution Approach 2:
The patent merges intra-FPGA timing analysis with inter-FPGA timing analysis into a unified graph-based framework. By combining local FPGA timing data with inter-chip connection timing data, the system achieves complete board-level synchronization analysis without the exponential complexity increase that would result from a monolithic model
Data Source
AI summary
The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.