Multi-Frequency Memory Interface with Segmented Controllers
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Solution Overview
Problem
Current memory systems face limitations in supporting multiple types of memories with different frequencies and addressing schemes, leading to reduced performance as they can only operate at the lowest frequency of the memory types, restricting the potential of faster memory types.
Innovation Solution
A multi-rank, multi-protocol memory interface that allows different types of memories to operate at distinct frequencies by using separate memory controllers and a multiplexer to select the appropriate controller based on the accessed rank, with a physical block generating multiple clocks to support various frequencies and addressing schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single memory interface supports multiple memory types with different frequencies, then memory system versatility is improved, but the interface can only operate at the lowest frequency of the memory types, reducing the speed of faster memory types
Solution Approach 1:
The memory interface is segmented into multiple independent memory controllers (first memory controller for DDR4, second memory controller for MRAM/PCM) that can operate at different frequencies simultaneously. Each controller is dedicated to specific memory types, allowing DDR4 to run at high speed while MRAM/PCM run at their native lower frequencies without mutual interference.
Solution Approach 2:
The patent introduces a new dimension of control by adding multiple memory controllers operating in parallel rather than trying to make a single controller adapt to different frequencies. This dimensional expansion allows the system to maintain multiple frequency domains simultaneously, resolving the frequency conflict between different memory types.
2Device complexity
If address pins are shared between different memory ranks, then device complexity is reduced, but the addressing scheme must be compatible across all ranks, limiting flexibility in supporting different memory types
Solution Approach 1:
Each memory controller acts as an intermediary between the shared address bus and its dedicated memory type. The controllers translate and adapt address signals according to the specific addressing scheme requirements of each memory type (DDR4 vs. MRAM/PCM), allowing shared address pins to support multiple addressing schemes without direct conflict.
Solution Approach 2:
The patent applies local quality by allowing different addressing schemes in different parts of the system (each memory controller's domain) while maintaining a unified shared address bus. Each memory controller is customized for its specific memory type's addressing requirements, while the overall system benefits from shared resources.
3Productivity
If a hybrid memory system uses multiple memory classes, then memory hierarchy benefits are achieved with reduced silicon die area, but the system is limited by the lowest frequency memory type
Solution Approach 1:
The hybrid memory system is segmented into independent frequency domains, with each memory controller managing its own frequency. This allows the DDR4 portion to operate at high frequency for performance-critical operations while MRAM/PCM operate at lower frequencies for non-volatile storage, with both functioning simultaneously without the entire system being bottlenecked to the lowest frequency.
Data Source
AI summary
A memory system is disclosed in the present disclosure. The memory system may include at least one first type of memory configured on at least one first rank and to operate at a first frequency, and at least one second type of memory configured on at least one second rank and to operate at a second frequency. The memory system may also include a physical block (PHY) configured to generate a first clock at the first frequency and a second clock at the second frequency.