Multi-Gate FeFET Memory Cell for Multi-Bit Storage Density
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Solution Overview
Problem
Conventional static random access memory (SRAM) devices are volatile and consume a large area, while existing ferroelectric random access memory (FeRAM) cells can only store a single bit of data, limiting their efficiency and density.
Innovation Solution
A multi-gate ferroelectric field-effect transistor (FeFET) memory cell is developed with multiple ferroelectric layers, each having a unique switching E-field, allowing for multiple threshold voltages and enabling the storage of multiple bits in a smaller area, utilizing BEOL or MEOL processes for manufacturing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM devices are used, then volatility is avoided (data retention), but area consumption increases significantly
Solution Approach 1:
The gate electrode is segmented into multiple independent gates (first gate, second gate, third gate) that can be independently controlled. This segmentation allows the memory cell to store multiple bits of data by utilizing different combinations of gate states, thereby increasing storage capacity without proportionally increasing the physical area of the memory cell.
Solution Approach 2:
Multiple ferroelectric layers are stacked vertically within the gate structure, with each layer capable of independent polarization states. This nested arrangement of multiple storage elements within a single vertical column enables multi-bit storage per cell location, effectively reducing the area required per stored bit while maintaining non-volatile characteristics.
2Area of stationary object
If single-bit FeRAM cells are used, then area is reduced, but storage capacity is limited to one bit
Solution Approach 1:
The gate electrode is divided into multiple independent gates (first gate, second gate, third gate) that can be independently controlled. This segmentation allows the memory cell to store multiple bits of data by utilizing different combinations of gate states, thereby increasing storage capacity without proportionally increasing the physical area of the memory cell.
Solution Approach 2:
The invention transitions from a planar single-bit structure to a vertical multi-layer structure by stacking multiple ferroelectric layers and corresponding gates in the vertical dimension. This dimensional change enables multiple bits of storage within the same footprint area, effectively multiplying storage capacity without increasing lateral area consumption.
3Quantity of substance
If multiple ferroelectric layers with unique switching E-fields are implemented, then multiple bits storage is enabled, but device complexity increases
Solution Approach 1:
Multiple gates share a common source-drain region and overlapping gate structures, allowing the same physical components to serve multiple functions. The first, second, and third gates can individually control different bits of data while sharing common structural elements, thereby reducing overall device complexity compared to having completely separate structures for each bit.
Solution Approach 2:
The invention merges multiple gate structures into a unified configuration where gates overlap and share common source-drain regions. This combining of structures reduces the total number of discrete components needed while maintaining the capability to store multiple bits, thereby managing device complexity through integration rather than proliferation of separate elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-gate FeFET memory cell achieves efficient storage of multiple bits in a reduced area, providing a more compact and efficient memory solution compared to conventional SRAM and single-bit FeRAM cells.
Implementation Method 1
A multi-gate ferroelectric field-effect transistor (FeFET) memory cell is developed with multiple ferroelectric layers, each having a unique switching E-field, allowing for multiple threshold voltages
Data Source
AI summary
A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.