Multi-Gated I/O Signal Sequencing to Prevent Power-Up Glitches
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Solution Overview
Problem
Integrated circuit (IC) I/O circuits face glitches during power ramp-up due to unstable signal transitions, leading to inefficiencies in electrical connections and data exchange.
Innovation Solution
A system for generating gated power-on control signals that uses a multi-gated I/O interface with a gating signals generator to control the enabling of output and input level shifters and drivers, ensuring signal stability before enabling subsequent components, thereby preventing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power ramp-up is performed rapidly to improve startup speed, then productivity is improved, but signal stability deteriorates causing glitches
Solution Approach 1:
The patent applies preliminary action by enabling the output level shifter before the output driver, and enabling the input buffer before the input level shifter. This sequencing ensures that signal paths are stabilized in advance before full power operation begins, preventing glitches during rapid power ramp-up while maintaining high startup speed
2Device complexity
If multiple components are enabled simultaneously to simplify control, then device complexity is reduced, but signal stability deteriorates causing glitches
Solution Approach 1:
The patent segments the I/O interface enabling process into distinct phases: first enabling the output level shifter, then the output driver, followed by the input buffer, and finally the input level shifter. This segmentation transforms a single complex simultaneous-enable operation into a sequence of simpler, controlled steps, reducing glitches while maintaining manageable control complexity
3Productivity
If level shifters and drivers are enabled during power ramp-up to improve startup time, then productivity is improved, but harmful factors increase due to glitching
Solution Approach 1:
The patent applies preliminary action by enabling the output level shifter before the output driver, and enabling the input buffer before the input level shifter. This sequencing ensures that signal paths are stabilized in advance before full power operation begins, preventing glitches during rapid power ramp-up while maintaining high startup speed
Data Source
AI summary
A method of generating multiple gating signals for a multi-gated input/output (I/O) system. The system includes an output level shifter and an output driver which are coupled in series between an output node of a core circuit and an external terminal of a corresponding system. The method includes: generating first and second gating signals having corresponding first and second waveforms, the first waveform transitioning from a non-enabling state to an enabling state before the second waveform transitions from the non-enabling state to the enabling state; receiving the first gating signal at the output level shifter; and receiving the second gating signal at the output driver.