Multi-Head Linked List Structure for One-Cycle RAM Data Reads
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Solution Overview
Problem
The existing linked list data structure in digital circuit design suffers from low data reading efficiency due to a read delay in Random Access Memory (RAM), requiring 3 to 4 clock cycles per data read, which is insufficient for high-bandwidth applications.
Innovation Solution
A multi-head linked list data structure with a control unit, write and read operation sub-link indicator units, and n sub-links, allowing data to be written and read in one clock cycle per sub-link, utilizing a free address management unit and pointer storage units to manage data and addresses efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the existing linked list data structure is used with sequential reading, then the data reading process is simple, but the data reading efficiency is low due to 3-4 clock cycles per read operation
Solution Approach 1:
The patent divides the traditional single linked list into multiple sub-links (n sub-links), where each sub-link maintains independent read/write pointers. This segmentation allows parallel access to different data elements across sub-links, enabling one piece of data to be read per clock cycle instead of requiring 3-4 cycles, thus resolving the contradiction between reading efficiency and structural complexity.
Solution Approach 2:
The patent introduces a new dimension by adding sub-link identifiers and organizing data in a multi-dimensional structure (sub-link index + position within sub-link). This dimensional expansion transforms the linear sequential access model into a parallel multi-channel access model, achieving high-speed data retrieval while managing complexity through structured organization.
2Speed
If the read delay of RAM is considered, then the existing linked list requires 3-4 clock cycles per read, but this results in insufficient bandwidth for high-performance applications
Solution Approach 1:
The patent performs preliminary actions by pre-organizing data into n sub-links with dedicated read/write pointers for each sub-link. This pre-structure enables direct access to data in any sub-link without sequential traversal, eliminating the 3-4 clock cycle delay and achieving one data read per clock cycle, thus resolving the speed-time loss contradiction.
Solution Approach 2:
The patent ensures continuous useful action by maintaining multiple active read/write operations simultaneously across different sub-links. While one sub-link is being read, another can be written to, eliminating idle clock cycles and achieving continuous data throughput at maximum bandwidth, resolving the contradiction between reading speed and time loss.
3Power
If one piece of data is read every four clock cycles in the existing linked list, then the system is simple to implement, but the bandwidth is limited to 128Gbps instead of the potential 512Gbps
Solution Approach 1:
The patent merges multiple sub-links into a unified multi-head linked list structure that operates as a single high-throughput system. By combining n sub-links with n read operations per clock cycle, the system achieves 512Gbps bandwidth (4x improvement), resolving the contradiction between implementation simplicity and bandwidth productivity.
Data Source
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AI summary
The present application relates to a linked list data structure and a data processing method therefor, a storage medium, and an electronic device. The linked list data structure comprises an RAM, an idle address management unit, and a multi-head linked list; the multi-head linked list comprises a control unit, a write operation sub-link indication unit, a read operation sub-link indication unit, and n sub-links; each sub-link comprises a sub-link length unit, a write pointer unit, and a read pointer unit. On the basis of the linked list data structure of the present application, a read command is initiated in each clock cycle by means of an n-head linked list, and data can be outputted in each clock cycle.