Multi-Height Cell Layout With Variable Channel Widths
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Solution Overview
Problem
Integrated circuits face challenges in achieving optimized performance and efficiency due to the limitations of device size reduction in semiconductor processes, where smaller devices offer high integration but limited performance, and larger devices provide high performance but at the cost of area and power consumption.
Innovation Solution
The design of integrated circuits incorporates multi-height cells with varying active pattern widths in multiple rows, where cells in one row have narrower active patterns and cells in adjacent rows have wider active patterns, allowing for optimized channel widths and performance by arranging high-speed cells in one row and other cells in another row, with buffer cells to manage transitions and optimize area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If device size is reduced to achieve high integration, then area efficiency is improved, but performance deteriorates
Solution Approach 1:
The patent applies local quality by creating different cell heights within the same integrated circuit. Specifically, first cells have a first height while second cells have a second height greater than the first height. This allows different regions of the circuit to have optimized device sizes - smaller devices in first cells for area efficiency and larger devices in second cells for performance - thereby resolving the contradiction between area efficiency and performance.
2Reliability
If larger devices are used to improve performance, then performance is improved, but area consumption increases
Solution Approach 1:
The patent segments the integrated circuit into multiple rows with different cell heights. Second cells with greater height (and thus larger effective channel width for better performance) are arranged in specific rows, while first cells with smaller height are arranged in other rows. This segmentation allows performance-critical sections to use larger devices while non-critical sections use smaller devices, optimizing the overall area utilization.
3Reliability
If multi-height cells are introduced to optimize performance, then performance is improved, but device complexity increases
Solution Approach 1:
The patent resolves the complexity issue by extending the solution into the vertical dimension. Instead of varying device size within a single plane (which would increase lateral complexity), the patent uses different cell heights in the vertical direction. This allows multiple performance levels to coexist without increasing the complexity of individual cell designs, as each cell type remains relatively simple but the overall circuit achieves performance optimization through vertical stratification.
Data Source
AI summary
An integrated circuit includes a first cell and a second cell respectively arranged in a first row and a second row that are adjacent to each other and extend in a first direction, and a third cell continuously arranged in the first row and the second row, wherein each of the first cell and the second cell comprises a first active pattern group including at least one active pattern that extends in the first direction and has a first conductivity type, the third cell comprises a second active pattern group including at least one active pattern that extends in the first direction in the first row and has the first conductivity type, and an effective channel width of the second active pattern group is greater than an effective channel width of the first active pattern group.