Multi-Height Flip-Flop Layout for Simpler IC Signal Routing

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Solution Overview

Problem

The increasing integration density of semiconductor ICs leads to complex signal routing between transistors, which is undesirable and requires approaches to alleviate the complexity.

Innovation Solution

Implementing flip-flops as multiple height cells that use the gate electrode for signal routing, allowing the flip-flops to be fabricated across multiple rows and reducing the complexity of signal paths by sharing gate electrodes for clock and data signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integration density of semiconductor ICs is increased, then more flip-flops can be included to enhance performance, but signal routing complexity between transistors becomes more complex

Engineering Contradiction:
Improveintegration densityVSAvoidsignal routing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The gate electrodes of adjacent latches are merged into a shared structure. Specifically, the first gate electrode is shared by the first latch and second latch, and the second gate electrode is shared by the third latch and fourth latch. This merging reduces the number of separate gate electrodes and simplifies signal routing while maintaining the functionality of multiple latches, thereby resolving the contradiction between integration density and signal routing complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared gate electrodes serve multiple functions by controlling multiple latches simultaneously. The first gate electrode controls both the first and second latches, while the second gate electrode controls both the third and fourth latches. This multi-functionality allows for higher integration density without proportionally increasing signal routing complexity, as the same gate electrode structure serves multiple logical units

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11742838B2Flip flop and design method for integrated circuit including the same
Publication Date: 2023.08.29 SAMSUNG ELECTRONICS CO LTD
  • US11742838B2 patent drawing
  • US11742838B2 patent drawing
  • US11742838B2 patent drawing

AI summary

A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.