Multi-Interface IC Test Mode with Simultaneous Power-Up
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Solution Overview
Problem
Integrated circuits with power islands face challenges in simultaneous testing without conflicting modes, leading to delays and increased manufacturing costs, while maintaining low power consumption and multi-interface capabilities.
Innovation Solution
The chip is designed to statically select one mode at manufacturing, allowing multiple power islands to be powered up simultaneously during testing, enabling thorough testing without mode conflicts and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple power islands are powered up simultaneously for testing, then testing thoroughness is improved, but mode conflicts occur between mutually exclusive interface modules
Solution Approach 1:
The patent applies preliminary action by setting specific voltage levels at bond pads before power-up to pre-determine which power island will be activated. This preliminary voltage configuration ensures that even though multiple power islands are simultaneously powered up during testing, only the intended interface module becomes operational, preventing mode conflicts before they can occur.
Solution Approach 2:
The patent changes the voltage parameter at bond pads to control power island selection. By adjusting voltage levels to specific thresholds during manufacturing testing, the system enables simultaneous power-up of multiple power islands while controlling which interface modules become active, thereby allowing comprehensive testing without harmful mode conflicts.
2Loss of energy
If quasi-static selection of power islands is used to configure control chip for external interface modes, then power consumption is reduced, but testing complexity increases
Solution Approach 1:
The patent applies universality by designing a single test program that can test all interface modules through controlled simultaneous power-up of multiple power islands. This universal testing approach eliminates the need for separate test programs for each interface mode, reducing testing complexity while maintaining the power consumption benefits of quasi-static power island selection.
Solution Approach 2:
The patent uses preliminary voltage configuration at bond pads to pre-set the operational state of different interface modules during testing. This preliminary action allows a single test program to systematically activate and test each interface module without requiring complex mode-switching logic, thereby reducing testing complexity while preserving low power consumption characteristics.
3Object-generated harmful factors
If statically selected power islands are powered off to avoid conflicts, then mode conflicts are prevented, but testing time increases due to sequential testing requirements
Solution Approach 1:
The patent applies preliminary action by configuring voltage levels at bond pads before power-up to pre-determine which power island becomes active. This allows multiple power islands to be simultaneously powered up during testing without causing mode conflicts, as the voltage configuration ensures only the intended interface module operates at any given time, thereby enabling parallel testing and reducing total testing time.
Solution Approach 2:
The patent changes voltage parameters at bond pads to enable controlled simultaneous activation of multiple power islands. By adjusting voltage levels to specific thresholds, the system allows comprehensive testing of all interface modules in parallel without harmful mode conflicts, significantly reducing testing time compared to sequential testing approaches.
Data Source
AI summary
A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.