Multi-Lane Clock Offsetting for Data Skew Control
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Solution Overview
Problem
Skew between multiple data lanes in data transmission can negatively impact data synchronization and merging, leading to packet corruption when the skew exceeds one system clock cycle.
Innovation Solution
Offsetting data lane clock signals by a fraction of a system clock cycle to limit skew to less than one cycle, using a clock reset stage to synchronize serial data at the receiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data lanes are used to increase data rate, then bandwidth is improved, but skew between lanes increases leading to synchronization problems
Solution Approach 1:
The patent applies preliminary action by offsetting the data lane clock signals by a fraction of a system clock cycle before data transmission begins. This pre-established timing offset ensures that skew between multiple data lanes is limited to less than one clock cycle, enabling reliable synchronization at the receiver without compromising the increased data rate achieved through multiple lanes.
2Reliability
If data lane clock signals are offset by a fraction of system clock cycle, then skew is limited to less than one cycle, but clock synchronization complexity increases
Solution Approach 1:
The patent changes the timing parameter of the data lane clock signals by introducing a fractional offset relative to the system clock cycle. This parameter adjustment limits the skew between lanes to less than one clock cycle, achieving reliable synchronization while using a systematic approach that can be implemented through clock management circuitry.
Data Source
AI summary
Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.