Multi-Layer Gate Trench Structure for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in effectively scaling integrated circuit density and controlling current while suppressing short channel effects, particularly in multi-gate transistors with complex gate structures.
Innovation Solution
The semiconductor device incorporates a substrate with defined PMOS and NMOS regions, featuring multiple nanosheets, gate spacers, and conductive layers with specific materials and configurations, including titanium aluminum nitride, titanium aluminum carbide, and titanium nitride, to enhance gate trench structures and improve electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistor with complex gate structure is used, then current control capability is improved, but device complexity increases
Solution Approach 1:
The gate electrode is segmented into multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) with different materials and functions. Each layer can be independently controlled, enabling separate control of channel regions while reducing overall structural complexity through modular design
Solution Approach 2:
Different portions of the gate electrode have different materials and properties: the first conductive layer has first work function, the second conductive layer has second work function, and the third conductive layer has third work function. This local quality variation enables optimized current control for different channel regions without requiring complete structural redesign
2Reliability
If gate length is increased to improve current control, then current control capability is improved, but device scaling is restricted
Solution Approach 1:
The patent transitions from controlling current through gate length extension to controlling current through vertical stacking of multiple conductive layers. The multi-layer gate structure provides additional control dimensions in the vertical direction, enabling current control without increasing horizontal gate length, thus maintaining device scalability
3Reliability
If multi-gate transistor is used to suppress short channel effect, then short channel effect suppression is improved, but device complexity increases
Solution Approach 1:
The gate electrode is divided into multiple conductive layers that can independently control different channel regions. This segmentation allows precise suppression of short channel effects at specific locations without requiring complex three-dimensional gate structures, thereby reducing overall device complexity while maintaining effectiveness
Solution Approach 2:
The patent controls short channel effects by adjusting work function parameters of different conductive layers rather than changing physical dimensions or complex geometries. By modifying electrical parameters (work functions) of existing structures, short channel effect suppression is achieved without increasing structural complexity
Data Source
AI summary
A semiconductor device includes an active pattern; gate spacers on the active pattern defining a gate trench; a gate insulating layer along a sidewall and a bottom surface of the gate trench; a first conductive layer on the gate insulating layer; a second conductive layer on the first conductive layer in the gate trench; a third conductive layer on the second conductive layer in the gate trench and including a first portion between parts of the second conductive layer, and a second portion on the first portion and in contact with an upper surface of the second conductive layer; and a capping pattern on the second and third conductive layers and including a portion between the gate insulating layer and the second portion, and in contact with a sidewall of the second portion, wherein a width of the second portion is greater than a width of the first portion.