Multi-Layer Mask Patterning for Defect-Resistant Active Patterns
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Solution Overview
Problem
Existing methods for fabricating semiconductor devices face challenges in preventing process defects during the etching process to form active patterns, particularly in multi-gate transistors with fin-shaped or nanowire-shaped silicon bodies.
Innovation Solution
A method involving the sequential formation of mask patterns and liner patterns on a substrate, followed by selective etching to create active patterns, including the use of multiple mask and liner layers to ensure precise pattern formation and prevent defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask material layers are sequentially formed to prevent process defects, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The mask structure is segmented into multiple functional layers (lower mask material layer, first mid mask material layer, second mid mask material layer, first upper mask material layer) with distinct purposes. Each layer performs specific functions in the pattern formation process, allowing precise control of different regions while maintaining overall manufacturing precision.
Solution Approach 2:
The patent introduces vertical layering (z-dimension) with multiple stacked mask material layers to solve planar pattern formation challenges. This multi-layer vertical structure enables independent patterning control at different heights, preventing process defects that cannot be addressed by single-layer masks.
2Manufacturing precision
If multiple etching steps are performed to form complex active patterns, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The lower mask pattern and mid mask patterns are formed in advance before the final upper mask patterning. These preliminary mask structures serve as templates and protection layers during subsequent etching steps, enabling precise active pattern formation while reducing the complexity of each individual etching operation.
Solution Approach 2:
Multiple mask patterns are nested vertically within the stacked mask material layers, with each layer containing specific pattern elements. The lower, mid, and upper mask layers are nested in the vertical direction, allowing sequential exposure and etching operations to proceed efficiently with each layer contributing to the final active pattern.
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region adjacent to the first region, sequentially forming, on an upper surface of the substrate, a lower mask material layer, a first mid mask material layer, a second mid mask material layer and a first upper mask material layer, forming a first mask pattern and a second mask pattern spaced apart from each other in a first horizontal direction on an upper surface of the first upper mask material layer on the first region of the substrate, forming a third mask pattern and a fourth mask pattern spaced apart from each other in the first horizontal direction on the upper surface of the first upper mask material layer on the second region of the substrate, forming a second upper mask material layer covering the first mask pattern, the second mask pattern, the third mask pattern, and the fourth mask pattern on the upper surface of the first upper mask material layer.