Multi-Layer Wiring Board Parasitic Capacitance for Laser Pulse Rise Time
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Solution Overview
Problem
In three-dimensional shape measurement devices using Time of Flight (ToF) technology, the rising period of light emitted from a laser is increased due to high inductance in the drive circuit, making it difficult to achieve high-frequency drive current flow, which affects measurement accuracy.
Innovation Solution
A light emitting device with a wiring board having a first and second wiring layer separated by an insulating layer, where the area of overlap between the second reference potential wire and the anode wire is larger than the area of overlap between the second reference potential wire and the first reference potential wire, utilizing low ESL capacitors and parasitic capacitance to reduce the rising period of the drive current pulse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional wiring layout is used, then manufacturing is simple, but inductance is high causing long rising period
Solution Approach 1:
The patent transitions from a single-plane wiring layout to a multi-layer wiring structure, utilizing the vertical dimension (z-axis) by introducing a second wiring layer adjacent to the first wiring layer via an insulating layer. This spatial reconfiguration reduces inductance by optimizing current path geometry without increasing manufacturing complexity
Solution Approach 2:
The patent divides the wiring system into multiple functional segments across two layers: the first wiring layer contains the anode wire and first reference potential wire, while the second wiring layer contains the second reference potential wire. This segmentation allows independent optimization of each wiring segment's position and function to minimize overall inductance
2Loss of time
If overlap area between reference potential wire and anode wire is increased, then capacitance increases reducing rising period, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different overlap area relationships to different wire pairs within the same wiring system. Specifically, the overlap area between the second reference potential wire and the anode wire is made larger than the overlap area between the second reference potential wire and the first reference potential wire. This local differentiation optimizes capacitance where needed while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the rising period of the drive current pulse, enabling the light source to emit light with a shorter rising time, thereby improving measurement accuracy in three-dimensional shape determination.
Implementation Method 1
it is appropriate to use more capacitive components between wires as a drive current for driving the laser compared with a case where the area of an overlap between a reference potential wire of the second wiring layer and an anode wire of the first wiring layer is smaller than the area of an overlap between the reference potential wire of the second wiring layer and a reference potential wire of the first wiring layer
Data Source
AI summary
A light emitting device includes a wiring board having a first wiring layer and a second wiring layer adjacent to the first wiring layer via an insulating layer, and a laser having a cathode electrode and an anode electrode, mounted on the wiring board, and driven through low-side driving. The first wiring layer includes a cathode wire connected to the cathode electrode, an anode wire connected to the anode electrode, and a first reference potential wire connected to a reference potential. The second wiring layer includes a second reference potential wire connected to the reference potential. An area of an overlap between the second reference potential wire and the anode wire is larger than an area of an overlap between the second reference potential wire and the first reference potential wire.