Multi-Level Column Decoder Parallel Write Mechanism
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Solution Overview
Problem
Conventional flash memory devices require multiple write cycles and are slow due to the need to activate only a single bit line for each write operation, resulting in lengthy write times for writing a block of data.
Innovation Solution
Incorporating a write buffer within a multi-level column decoder allows multiple memory cells associated with a single write driver to be written in parallel, reducing the number of write cycles and increasing write operation speed by enabling simultaneous activation of multiple bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If only a single bit line is activated for each write operation in conventional flash memory devices, then the write operation is simple to control, but the write speed is slow and multiple write cycles are required
Solution Approach 1:
The column decoder is divided into multiple levels (first level and second level) that can independently activate different groups of bit lines. This segmentation allows multiple bit lines to be activated simultaneously while maintaining organized control, resolving the contradiction between write speed and control complexity
Solution Approach 2:
The patent introduces a multi-level column decoder structure that adds a dimensional layer to the bit line activation process. Instead of a single-level decoder activating one bit line at a time, the multi-level structure enables parallel activation of multiple bit lines through hierarchical control, thereby increasing write speed without proportionally increasing control complexity
2Productivity
If multiple bit lines are activated simultaneously to write multiple memory cells in parallel, then the write operation speed increases, but the control complexity and decoder structure become more complex
Solution Approach 1:
The column decoder is segmented into multiple levels where each level controls a subset of bit lines. This segmentation allows parallel activation of multiple bit lines (increasing productivity) while distributing the control logic across multiple manageable levels (managing complexity)
Solution Approach 2:
The multi-level column decoder provides dynamic control over bit line activation. Different combinations of bit lines can be activated simultaneously by coordinating the first and second level decoders, enabling flexible parallel write operations that increase throughput while maintaining manageable control structure
3Reliability
If multiple write cycles are used to write a block of data, then each individual write operation is reliable and complete, but the total write time becomes lengthy
Solution Approach 1:
The multi-level column decoder is pre-configured to enable simultaneous activation of multiple bit lines. This preliminary structural arrangement allows multiple memory cells to be written in parallel in a single write cycle, reducing total write time while maintaining the reliability of each individual write operation through proper bias conditioning
Solution Approach 2:
By enabling parallel write operations through the multi-level column decoder, the system maintains continuous useful action across multiple memory cells simultaneously. This eliminates the idle time between sequential write cycles while ensuring each write operation completes reliably with proper voltage and current conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the time required to write a block of data by allowing multiple data bits to be written in parallel, thereby enhancing the speed and efficiency of the write operation.
Implementation Method 1
programming of the memory cell, or writing data to the memory cell, is accomplished by transferring charge carriers from the semiconductor substrate (the source or the drain) to the floating gate by tunneling through the thin gate oxide layer
Data Source
AI summary
A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of write operation.